Quartus® Prime Pro Edition User Guide: Getting Started

Download PDF
ID 683463
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Introduction to Quartus® Prime Pro Edition 2. Planning FPGA Design for RTL Flow 3. Selecting a Starting Point for Your Quartus® Prime Pro Edition Project 4. Working With Intel® FPGA IP Cores 5. Managing Quartus® Prime Projects A. Next Steps After Getting Started B. Using the Design Space Explorer II C. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started D. Quartus® Prime Pro Edition User Guides
1. Introduction to Quartus® Prime Pro Edition x
1.1. Before You Begin
1.1. Before You Begin x
1.1.1. Prerequisite Knowledge and Training 1.1.2. Navigate Content Through Tasks 1.1.3. Acronyms
2. Planning FPGA Design for RTL Flow x
2.1. Design Planning 2.2. Selecting the Design Methodology 2.3. Related Trainings
2.2. Selecting the Design Methodology x
2.2.1. Flat Design Vs. Incremental Block-based Design 2.2.2. Partial Reconfiguration Design
3. Selecting a Starting Point for Your Quartus® Prime Pro Edition Project x
3.1. Creating a New FPGA Design Project 3.2. Migrating Projects from Other Quartus® Prime Editions to Quartus® Prime Pro Edition 3.3. Migrating Your AMD* Vivado* Project to Quartus® Prime Pro Edition 3.4. Migrating Projects Across Operating Systems 3.5. Migrating Project From One Device to Another 3.6. Related Trainings
3.1. Creating a New FPGA Design Project x
3.1.1. Using the Board-Aware Flow
3.1.1. Using the Board-Aware Flow x
3.1.1.1. Creating a New Project from a Design Example 3.1.1.2. Specifying a Target Board for the Project
3.1.1.1. Creating a New Project from a Design Example x
3.1.1.1.1. Family, Device & Board Settings 3.1.1.1.2. Accessing Pre-Installed Design Examples 3.1.1.1.3. Accessing Online Design Examples 3.1.1.1.4. Accessing Downloaded Design Examples
3.1.1.1.3. Accessing Online Design Examples x
3.1.1.1.3.1. Internet Connectivity Options 3.1.1.1.3.2. Design Examples Options
3.2. Migrating Projects from Other Quartus® Prime Editions to Quartus® Prime Pro Edition x
3.2.1. Keeping Pro Edition Project Files Separate 3.2.2. Upgrading Project Assignments and Constraints 3.2.3. Upgrading IP Cores and Platform Designer Systems 3.2.4. Upgrading Non-Compliant Design RTL
3.2.2. Upgrading Project Assignments and Constraints x
3.2.2.1. Modifying Entity Name Assignments 3.2.2.2. Resolving Timing Constraint Entity Names 3.2.2.3. Verifying Generated Node Name Assignments 3.2.2.4. Replace Logic Lock (Standard) Regions 3.2.2.5. Modifying Signal Tap Logic Analyzer Files 3.2.2.6. Removing References to .qip Files 3.2.2.7. Removing Unsupported Feature Assignments
3.2.2.4. Replace Logic Lock (Standard) Regions x
3.2.2.4.1. Logic Lock Region Assignment Examples
3.2.4. Upgrading Non-Compliant Design RTL x
3.2.4.1. Verifying Verilog Compilation Unit 3.2.4.2. Updating Entity Auto-Discovery 3.2.4.3. Ensuring Distinct VHDL Namespace for Each Library 3.2.4.4. Removing Unsupported Parameter Passing 3.2.4.5. Removing Unsized Constant from WYSIWYG Instantiation 3.2.4.6. Removing Non-Standard Pragmas 3.2.4.7. Declaring Objects Before Initial Values 3.2.4.8. Confining SystemVerilog Features to SystemVerilog Files 3.2.4.9. Avoiding Assignment Mixing in Always Blocks 3.2.4.10. Avoiding Unconnected, Non-Existent Ports 3.2.4.11. Avoiding Invalid Parameter Ranges 3.2.4.12. Updating Verilog HDL and VHDL Type Mapping 3.2.4.13. Converting Symbolic BDF Files to Acceptable File Formats
3.2.4.1. Verifying Verilog Compilation Unit x
3.2.4.1.1. Verilog HDL Configuration Instantiation
3.4. Migrating Projects Across Operating Systems x
3.4.1. Migrating Design Files and Libraries 3.4.2. Design Library Migration Guidelines
3.4.1. Migrating Design Files and Libraries x
3.4.1.1. Use Relative Paths
4. Working With Intel® FPGA IP Cores x
4.1. IP Catalog and Parameter Editor 4.2. Installing and Licensing Intel® FPGA IP Cores 4.3. IP General Settings 4.4. Adding IP to IP Catalog 4.5. Best Practices for Intel® FPGA IP 4.6. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 4.7. IP Core Generation Output ( Quartus® Prime Pro Edition) 4.8. Scripting IP Core Generation 4.9. Modifying an IP Variation 4.10. Upgrading IP Cores 4.11. Simulating Intel® FPGA IP Cores 4.12. Generating Simulation Files for Platform Designer Systems and IP Variants 4.13. Synthesizing IP Cores in Other EDA Tools 4.14. Instantiating IP Cores in HDL 4.15. Support for the IEEE 1735 Encryption Standard 4.16. Related Trainings and Resources
4.1. IP Catalog and Parameter Editor x
4.1.1. The Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores x
4.2.1. Intel® FPGA IP Evaluation Mode
4.2.1. Intel® FPGA IP Evaluation Mode x
4.2.1.1. Intel FPGA IP Versioning 4.2.1.2. Checking the IP License Status
4.6. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) x
4.6.1. Applying Preset Parameters for Specific Applications 4.6.2. Customizing IP Presets
4.6.1. Applying Preset Parameters for Specific Applications x
4.6.1.1. Viewing, Applying, and Deleting IP Presets
4.6.2. Customizing IP Presets x
4.6.2.1. Defining Preset Pin Assignments
4.6.2.1. Defining Preset Pin Assignments x
4.6.2.1.1. Defining Preset Pin Assignments in Pin Assignments Tab 4.6.2.1.2. Defining Preset Pin Assignments in a Pin File
4.10. Upgrading IP Cores x
4.10.1. Upgrading IP Cores at Command-Line 4.10.2. Migrating IP Cores to a Different Device 4.10.3. Troubleshooting IP or Platform Designer System Upgrade
4.11. Simulating Intel® FPGA IP Cores x
4.11.1. Generating IP Simulation Files 4.11.2. Scripting IP Simulation
4.11.2. Scripting IP Simulation x
4.11.2.1. Generating a Combined Simulator Setup Script
4.14. Instantiating IP Cores in HDL x
4.14.1. Example Top-Level Verilog HDL Module 4.14.2. Example Top-Level VHDL Module
5. Managing Quartus® Prime Projects x
5.1. Viewing Basic Project Information 5.2. Managing Project Settings 5.3. Viewing Parameter Settings From the Project Navigator 5.4. Managing Logic Design Files 5.5. Managing Timing Constraints 5.6. Integrating Other EDA Tools 5.7. Exporting Compilation Results 5.8. Archiving Projects 5.9. Command-Line Interface 5.10. Related Trainings
5.1. Viewing Basic Project Information x
5.1.1. Using the Compilation Dashboard 5.1.2. Exploring Quartus® Prime Project Contents 5.1.3. Viewing Design Hierarchy and Adding Missing Source Files 5.1.4. Viewing Project Reports 5.1.5. Viewing Project Messages
5.1.2. Exploring Quartus® Prime Project Contents x
5.1.2.1. Project File Best Practices
5.1.5. Viewing Project Messages x
5.1.5.1. Viewing Synthesis Warning Messages 5.1.5.2. Suppressing Message Display 5.1.5.3. Promoting Critical Warnings to Errors
5.4. Managing Logic Design Files x
5.4.1. Including Design Libraries 5.4.2. Creating a Project Copy
5.7. Exporting Compilation Results x
5.7.1. Exporting a Version-Compatible Compilation Database 5.7.2. Importing a Version-Compatible Compilation Database 5.7.3. Creating a Design Partition 5.7.4. Exporting a Design Partition 5.7.5. Reusing a Design Partition 5.7.6. Viewing Quartus Database File Information 5.7.7. Clearing Compilation Results
5.7.6. Viewing Quartus Database File Information x
5.7.6.1. QDB File Attribute Types
5.8. Archiving Projects x
5.8.1. Manually Adding Files To Archives 5.8.2. Archiving Projects for Service Requests 5.8.3. Archiving Projects for External Revision Control 5.8.4. Creating Database-Only Archives
5.8.3. Archiving Projects for External Revision Control x
5.8.3.1. Project Files to Include In External Revision Control
5.9. Command-Line Interface x
5.9.1. Project Revision Commands 5.9.2. Project Archive Commands 5.9.3. Project Database Commands
5.9.3. Project Database Commands x
5.9.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
A. Next Steps After Getting Started x
A.1. Additional Resources A.2. Training
B. Using the Design Space Explorer II x
B.1. Optimizing Project Settings B.2. Running DSE II B.3. Setting Up Remote Farm Using Design Space Explorer II
B.1. Optimizing Project Settings x
B.1.1. Optimizing Settings with Design Space Explorer II B.1.2. Optimizing Settings with Project Revisions B.1.3. Back-Annotating Optimized Assignments
B.1.1. Optimizing Settings with Design Space Explorer II x
B.1.1.1. DSE II Computing Resources B.1.1.2. DSE II Optimization Parameters B.1.1.3. DSE II Result Management
Answers to Top FAQs
1. Introduction to Quartus® Prime Pro Edition
2. Planning FPGA Design for RTL Flow
3. Selecting a Starting Point for Your Quartus® Prime Pro Edition Project
4. Working With Intel® FPGA IP Cores
5. Managing Quartus® Prime Projects
A. Next Steps After Getting Started
B. Using the Design Space Explorer II
C. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started
D. Quartus® Prime Pro Edition User Guides

3.2.4.8. Confining SystemVerilog Features to SystemVerilog Files

Quartus® Prime Pro Edition synthesis does not allow SystemVerilog features in Verilog HDL files. Other Quartus software products allow use of a subset of SystemVerilog (.sv) features in Verilog HDL (.v) design files. To avoid syntax errors in Quartus® Prime Pro Edition, allow only SystemVerilog features in Verilog HDL files.
To use SystemVerilog features in your existing Verilog HDL files, rename your Verilog HDL (.v) files as SystemVerilog (.sv) files. Alternatively, you can set the file type in the .qsf, as shown in the following example: 
set_global_assignment -name SYSTEMVERILOG_FILE <file>.v
Table 19.  SystemVerilog Feature Differences
Other Quartus Software Products Quartus® Prime Pro Edition
From the Example RTL, synthesis interprets $clog2 in a .v file, even though the Verilog LRM does not define the $clog2 feature. Other Quartus software products allow other SystemVerilog features in .v files. From the Example RTL, synthesis generates a syntax error for detection of any non-Verilog HDL construct in .v files. Quartus® Prime Pro Edition synthesis honors SystemVerilog features only in .sv files.

Example RTL:

localparam num_mem_locations = 1050;
wire mem_addr [$clog2(num_mem_locations)-1 : 0];
Level Two Title