Intel® Quartus® Prime Pro Edition User Guide: Getting Started

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ID 683463
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® Quartus® Prime Pro Edition 2. Managing Intel® Quartus® Prime Projects 3. Design Planning 4. Introduction to Intel® FPGA IP Cores 5. Migrating to Intel® Quartus® Prime Pro Edition A. Intel® Quartus® Prime Pro Edition User Guides 6. Document Archives
1. Introduction to Intel® Quartus® Prime Pro Edition x
1.1. Selecting an Intel® Quartus® Prime Software Edition 1.2. Introduction to Intel® Quartus® Prime Pro Edition Revision History
2. Managing Intel® Quartus® Prime Projects x
2.1. Viewing Basic Project Information 2.2. Intel® Quartus® Prime Project Contents 2.3. Managing Project Settings 2.4. Managing Logic Design Files 2.5. Managing Timing Constraints 2.6. Integrating Other EDA Tools 2.7. Exporting Compilation Results 2.8. Migrating Projects Across Operating Systems 2.9. Archiving Projects 2.10. Command-Line Interface 2.11. Managing Projects Revision History
2.1. Viewing Basic Project Information x
2.1.1. Using the Compilation Dashboard 2.1.2. Viewing Project Reports 2.1.3. Viewing Project Messages
2.1.3. Viewing Project Messages x
2.1.3.1. Viewing Synthesis Warning Messages 2.1.3.2. Suppressing Message Display 2.1.3.3. Promoting Critical Warnings to Errors
2.2. Intel® Quartus® Prime Project Contents x
2.2.1. Project File Best Practices
2.3. Managing Project Settings x
2.3.1. Specifying the Target Device or Board 2.3.2. Optimizing Project Settings
2.3.2. Optimizing Project Settings x
2.3.2.1. Optimize Settings with Design Space Explorer II 2.3.2.2. Optimize Settings with Project Revisions 2.3.2.3. Back-Annotate Optimized Assignments
2.4. Managing Logic Design Files x
2.4.1. Including Design Libraries 2.4.2. Creating a Project Copy
2.7. Exporting Compilation Results x
2.7.1. Exporting a Version-Compatible Compilation Database 2.7.2. Importing a Version-Compatible Compilation Database 2.7.3. Creating a Design Partition 2.7.4. Exporting a Design Partition 2.7.5. Reusing a Design Partition 2.7.6. Viewing Quartus Database File Information 2.7.7. Clearing Compilation Results
2.7.6. Viewing Quartus Database File Information x
2.7.6.1. QDB File Attribute Types
2.8. Migrating Projects Across Operating Systems x
2.8.1. Migrating Design Files and Libraries 2.8.2. Design Library Migration Guidelines
2.8.1. Migrating Design Files and Libraries x
2.8.1.1. Use Relative Paths
2.9. Archiving Projects x
2.9.1. Manually Adding Files To Archives 2.9.2. Archiving Projects for Service Requests 2.9.3. Archiving Projects for External Revision Control 2.9.4. Creating Database-Only Archives
2.9.3. Archiving Projects for External Revision Control x
2.9.3.1. Project Files to Include In External Revision Control
2.10. Command-Line Interface x
2.10.1. Project Revision Commands 2.10.2. Project Archive Commands 2.10.3. Project Database Commands
2.10.3. Project Database Commands x
2.10.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
3. Design Planning x
3.1. Design Planning 3.2. Create a Design Specification and Test Plan 3.3. Plan for the Target Device 3.4. Plan for Intellectual Property Cores 3.5. Plan for Standard Interfaces 3.6. Plan for Device Programming 3.7. Plan for Device Power Consumption 3.8. Plan for Interface I/O Pins 3.9. Plan for other EDA Tools 3.10. Plan for On-Chip Debugging Tools 3.11. Plan HDL Coding Styles 3.12. Plan for Hierarchical and Team-Based Designs 3.13. Design Planning Revision History
3.3. Plan for the Target Device x
3.3.1. Device Migration Planning
3.8. Plan for Interface I/O Pins x
3.8.1. Simultaneous Switching Noise Analysis
3.9. Plan for other EDA Tools x
3.9.1. Third-Party Synthesis Tools 3.9.2. Third-Party Simulation Tools
3.11. Plan HDL Coding Styles x
3.11.1. Design Recommendations 3.11.2. Recommended HDL Coding Styles 3.11.3. Managing Metastability
3.12. Plan for Hierarchical and Team-Based Designs x
3.12.1. Flat Compilation without Design Partitions
4. Introduction to Intel® FPGA IP Cores x
4.1. IP Catalog and Parameter Editor 4.2. Installing and Licensing Intel® FPGA IP Cores 4.3. IP General Settings 4.4. Adding IP to IP Catalog 4.5. Best Practices for Intel® FPGA IP 4.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 4.7. Modifying an IP Variation 4.8. Upgrading IP Cores 4.9. Simulating Intel® FPGA IP Cores 4.10. Simulating Platform Designer Systems 4.11. Synthesizing IP Cores in Other EDA Tools 4.12. Instantiating IP Cores in HDL 4.13. Support for the IEEE 1735 Encryption Standard 4.14. Introduction to Intel FPGA IP Cores Revision History
4.1. IP Catalog and Parameter Editor x
4.1.1. The Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores x
4.2.1. Intel® FPGA IP Evaluation Mode
4.2.1. Intel® FPGA IP Evaluation Mode x
4.2.1.1. Intel FPGA IP Versioning 4.2.1.2. Checking the IP License Status
4.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
4.6.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 4.6.2. Scripting IP Core Generation
4.8. Upgrading IP Cores x
4.8.1. Upgrading IP Cores at Command-Line 4.8.2. Migrating IP Cores to a Different Device 4.8.3. Troubleshooting IP or Platform Designer System Upgrade
4.9. Simulating Intel® FPGA IP Cores x
4.9.1. Generating IP Simulation Files 4.9.2. Scripting IP Simulation
4.9.2. Scripting IP Simulation x
4.9.2.1. Generating a Combined Simulator Setup Script ( Intel® Quartus® Prime Pro Edition)
4.12. Instantiating IP Cores in HDL x
4.12.1. Example Top-Level Verilog HDL Module 4.12.2. Example Top-Level VHDL Module
5. Migrating to Intel® Quartus® Prime Pro Edition x
5.1. Keep Pro Edition Project Files Separate 5.2. Upgrade Project Assignments and Constraints 5.3. Upgrade IP Cores and Platform Designer Systems 5.4. Upgrade Non-Compliant Design RTL 5.5. Migrating to Intel® Quartus® Prime Pro Edition Revision History
5.2. Upgrade Project Assignments and Constraints x
5.2.1. Modify Entity Name Assignments 5.2.2. Resolve Timing Constraint Entity Names 5.2.3. Verify Generated Node Name Assignments 5.2.4. Replace Logic Lock (Standard) Regions 5.2.5. Modify Signal Tap Logic Analyzer Files 5.2.6. Remove References to .qip Files 5.2.7. Remove Unsupported Feature Assignments
5.2.4. Replace Logic Lock (Standard) Regions x
5.2.4.1. Logic Lock Region Assignment Examples
5.4. Upgrade Non-Compliant Design RTL x
5.4.1. Verify Verilog Compilation Unit 5.4.2. Update Entity Auto-Discovery 5.4.3. Ensure Distinct VHDL Namespace for Each Library 5.4.4. Remove Unsupported Parameter Passing 5.4.5. Remove Unsized Constant from WYSIWYG Instantiation 5.4.6. Remove Non-Standard Pragmas 5.4.7. Declare Objects Before Initial Values 5.4.8. Confine SystemVerilog Features to SystemVerilog Files 5.4.9. Avoid Assignment Mixing in Always Blocks 5.4.10. Avoid Unconnected, Non-Existent Ports 5.4.11. Avoid Illegal Parameter Ranges 5.4.12. Update Verilog HDL and VHDL Type Mapping
5.4.1. Verify Verilog Compilation Unit x
5.4.1.1. Verilog HDL Configuration Instantiation
1. Introduction to Intel® Quartus® Prime Pro Edition
2. Managing Intel® Quartus® Prime Projects
3. Design Planning
4. Introduction to Intel® FPGA IP Cores
5. Migrating to Intel® Quartus® Prime Pro Edition
A. Intel® Quartus® Prime Pro Edition User Guides
6. Document Archives

4.10. Simulating Platform Designer Systems

You can simulate your Platform Designer system in a supported third-party simulator to verify and debug system operation. When you Generate HDL for your system or IP component, Platform Designer can also optionally generate the corresponding simulation models, along with scripts to set up your supported simulator.

To generate the simulation model and simulator setup scripts for your Platform Designer system or component, follow these steps:

  1. In Platform Designer, click Generate > Generate HDL. The Generation dialog box appears.
  2. Under Simulation, specify Verilog or VHDL for the Create simulation model option.
  3. Turn on or off the ModelSim, VCS-MX, VCS, Riviera-Pro, or Xcelium option to generate simulator setup scripts for the simulation tool. If you turn on no simulator options, the scripts generate for all simulators.
  4. Click the Generate button. Platform Designer generates the simulation models and setup scripts for your system or IP component in the following directory:
    <top-level system name>/<system name>/<sim>/<simulator>
    Figure 57. Simulation Options in Generation Dialog Box
    Figure 58. Generated Simulation Files Location

By default, Platform Designer generates the simulation scripts for the currently loaded system and all subsystems. Alternatively, you can open a subsystem to generate a simulation script only for that subsystem.

You can use scripts to compile the required device libraries and system design files in the correct order and elaborate or load the top-level system for simulation.

Table 20.  Simulation Script VariablesThe simulation scripts provide variables that allow flexibility in your simulation environment.
Variable Description
TOP_LEVEL_NAME If the testbench Platform Designer system is not the top‑level instance in your simulation environment because you instantiate the Platform Designer testbench within your own top-level simulation file, set the TOP_LEVEL_NAME variable to the top-level hierarchy name.
QSYS_SIMDIR If the simulation files generated by Platform Designer are not in the simulation working directory, use the QSYS_SIMDIR variable to specify the directory location of the Platform Designer simulation files.
QUARTUS_INSTALL_DIR Points to the Quartus installation directory that contains the device family library.

Top-Level Simulation HDL File for a Testbench System

The example below shows the pattern_generator_tb generated for a Platform Designer system called pattern_generator. The top.sv file defines the top-level module that instantiates the pattern_generator_tb simulation model, as well as a custom SystemVerilog test program with BFM transactions, called test_program. 

module top();
 pattern_generator_tb tb();
 test_program pgm();
endmodule
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