3.10. Error Interface
Stratix 10 | Arria 10, Stratix V | Comments |
---|---|---|
tx_par_err |
tx_par_err[1:0] |
Stratix 10: The TX Transaction Layer or TX Data Link Layer asserts tx_par_err to indicate a parity error. Arria 10, Stratix V: The following encodings are defined:
|
derr_uncor_ext_rcv |
Not supported |
Stratix 10: When asserted, indicates an uncorrectable 2-bit ECC error in the RX buffer. Arria 10, Stratix V: Not supported. |
Not supported |
cfg_par_err |
Stratix 10: Not supported. Arria 10, Stratix V: Indicates a parity error in a TLP routed to the internal Configuration Space. This error is also logged in the Vendor Specific Extended Capability Internal Error register. You must reset the IP core if this error occurs. |