3.6. Avalon-MM Master Interfaces
Stratix 10 | Arria 10, Stratix V | Comments |
---|---|---|
rxm_bar_* |
Rxm* |
Signal names differ but functionality is the same unless otherwise noted below. |
rxm_bar_<m>_writedata_o[<n>-1:0] rxm_bar_<m>_readdata_o[<n>-1:0] |
RxmDataWrite_<m>_o[<n>-1:0] RxmReadData_<m>_o[<n>-1:0] |
<m> is the BAR number, 0-5 <n> is the width of the bus Stratix 10: All BARs can be bursting, non-bursting, or disabled.<n> has the following values:
Arria 10, Stratix V: Every BAR can be non-bursting or disabled. For non-bursting BARs <n> = 32. Only BAR2 supports bursting. If BAR2 is bursting <n>=128 for a 128-bit Avalon-MM interface. <n>=256 for a 256-bit Avalon-MM interface. |
rxm_bar_<m>_byteenable_o[<n>-1:0] |
RxmByteEnable_<m>_o[<n>-1:0] |
<m> is the BAR number, 0-5. <n> is the width of the bus. Stratix 10: All BARs can be bursting, non-bursting, or disabled. <n> has the following values:
Arria 10, Stratix V: Every BAR can be non-bursting or disabled. For non-bursting BARs <n> = 4. BAR2 only supports bursting. If BAR2 is bursting <n>=16 for a 128-bit Avalon-MM interface. <n>=32 for a 256-bit Avalon-MM interface. |