Intel® Advanced Link Analyzer: User Guide

Download PDF
ID 683448
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Advanced Link Analyzer Overview 2. Functional Description 3. Tutorial: PCI Express* 8GT 4. Document Revision History for Intel® Advanced Link Analyzer User Guide
1. Intel® Advanced Link Analyzer Overview x
1.1. System Requirements 1.2. Installation 1.3. Program and File Types 1.4. Accessing the User Guide
2. Functional Description x
2.1. Intel® Advanced Link Analyzer Control Module 2.2. Intel® Advanced Link Analyzer Data Viewer Module 2.3. Intel® Advanced Link Analyzer Channel Viewer Module 2.4. Intel® Advanced Link Analyzer Batch Simulation Controller 2.5. Intel® Advanced Link Analyzer Channel Designer
2.1. Intel® Advanced Link Analyzer Control Module x
2.1.1. Constructing Communication Links in the Link Designer Module 2.1.2. Link and Simulation Setting 2.1.3. Transmitter Setting 2.1.4. Receiver Setting 2.1.5. IBIS-AMI Wrapper 2.1.6. Channel Setting 2.1.7. Batch Channel Simulation Configuration 2.1.8. Crosstalk Aggressor Transmitter Setting 2.1.9. Repeater and Retimer Configurations 2.1.10. Noise Source Link Component 2.1.11. System Options 2.1.12. Project Management Functions 2.1.13. Archiving and Unarchiving Projects 2.1.14. Device Model Importer 2.1.15. Analysis Functions and Pre-Simulation and Pre-Analysis Checklists 2.1.16. COM Analysis 2.1.17. Link Builder
2.1.3. Transmitter Setting x
2.1.3.1. Jitter/Noise Component 2.1.3.2. Transmitter Options 2.1.3.3. Characterization Data Access 2.1.3.4. IBIS-AMI Transmitter Configuration 2.1.3.5. Pulse Fitting Analysis 2.1.3.6. SNDR Analysis 2.1.3.7. Jnu/Jrms/EOJ Analysis 2.1.3.8. Clock Path Custom Transmitter
2.1.4. Receiver Setting x
2.1.4.1. Jitter/Noise Setting 2.1.4.2. Characterization Data Access 2.1.4.3. Receiver Options 2.1.4.4. IBIS-AMI Receiver Configuration 2.1.4.5. Custom Receiver With Input Clock
2.1.9. Repeater and Retimer Configurations x
2.1.9.1. Repeater/Retimer RX Configuration 2.1.9.2. Repeater/Retimer TX Configuration
2.3. Intel® Advanced Link Analyzer Channel Viewer Module x
2.3.1. Channel Plot Panel 2.3.2. Channel List Panel 2.3.3. Plot Option Panel
2.3.3. Plot Option Panel x
2.3.3.1. S-parameter Mode Panel 2.3.3.2. Plot Configuration Panel 2.3.3.3. Options
3. Tutorial: PCI Express* 8GT x
3.1. Methodology 3.2. Setup and Initialization 3.3. Analysis
3.2. Setup and Initialization x
3.2.1. Setting Up the Control Module 3.2.2. Constructing the Channel 3.2.3. Completing the System
1. Intel® Advanced Link Analyzer Overview
2. Functional Description
3. Tutorial: PCI Express* 8GT
4. Document Revision History for Intel® Advanced Link Analyzer User Guide

2.1.3.1. Jitter/Noise Component

The Jitter/Noise panel allows you to input or import jitter and noise parameters. Intel® Advanced Link Analyzer provides extensive transmitter jitter and noise modeling and configuration capabilities.

The following figure shows the jitter decomposition diagram and the breakdown of jitter components:

Figure 19. Transmitter Jitter Decomposition

Transmitter Jitter Decomposition

Table 10.  Transmitter Intrinsic Jitter and Noise Types

Name

Description

Unit

Support in Intel® Advanced Link Analyzer

Comments

DJ

Deterministic Jitter

Unit Interval (UI)

Yes

DJ can be generated using a uniform distribution, dual-Dirac, or truncated Gaussian method. Select the DJ generation method in the Transmitter Jitter/Noise Options Window. The default DJ method is dual-Dirac. DJ consists of periodic jitter, bounded uncorrelated jitter, inter-symbol interference, and duty-cycle distortion. The DJ value is used in the simulation when the DJ/RJ-DN/RN method is selected.

ISI

Inter-Symbol Interference

UI

Yes

ISI can be generated using a uniform distribution, dual-Dirac, or truncated Gaussian method. Select the ISI generation method in the Transmitter Jitter/Noise Options Window. The default ISI method is dual-Dirac.

DCD

Duty Cycle Distortion

UI

Yes

The DCD parameter models two types of jitter: Positive pulse width jitter (PPWJ) and Clock DCD. The PPWJ shortens or lengthens the logic 1 waveform. The Clock DCD emulates distorted clock waveform effects on the transmitter output waveform. You can select the DCD generation method in the Transmitter Jitter/Noise Options Window. The default DCD method is PPWJ – (shortened positive waveform).

BUJ

Bounded Uncorrelated Jitter

UI

Yes

Same as Deterministic Jitter. The default BUJ method is Uniform distribution.

RJ

Random Jitter

UI-RMS or ps-RMS

Yes

RJ is assumed to be Gaussian. RJ can be specified in either pico-second (ps-RMS) or UI-RMS.

SJ

Sinusoidal Jitter

Amplitude: UI

Frequency: MHz

Yes

Sinusoidal jitter can be specified with amplitude and frequency.

DN

Deterministic Noise

mV

Yes

DN can be generated using a uniform distribution, dual-Dirac, or truncated Gaussian method. You can select the DN generation method in the Transmitter Jitter/Noise Options Window. The default DN method is uniform.

BUN

Bound Uncorrelated Noise

mV

Yes

Same as DN. The default method is the Truncated Gaussian method with a Peak-to-RMS ratio of 14. You can select the BUN generation method and parameters in the Transmitter Jitter/Noise Options Window.

RN

Random Noise

mV-RMS

Yes

RN is assumed to be Gaussian.

Jitter PDF

Jitter Probability Density Function (PDF)

Jitter amplitude, Probability (Jitter amplitude can be in absolute time or UI (unit interval) unit)

Yes

Jitter PDF defines the jitter probability density function. The input format is jitter amplitude in second and probability. The following is a jitter PDF example:

-5e-12 1e-10

-4e-12 3e-7

-3e-12 1e-4

-2e-12 1e-2

-1e-12 0.29

0 0.4

1e-12 0.29

2e-12 1e-2

3e-12 1e-4

4e-12 3e-7

5e-12 1e-10

Noise PDF

Noise Probability Density Function

Noise amplitude, Probability

Yes

Noise PDF defines the noise probability density function. The input format is Noise amplitude in volt and probability. The following is a noise PDF example:

-50e-3 1e-10

-40e-3 3e-7

-30e-3 1e-4

-20e-3 1e-2

-10e-3 0.29

0 0.4

10e-3 0.29

20e-3 1e-2

30e-3 1e-4

40e-3 3e-7

50e-3 1e-10

CMN

Common Mode Noise

mV-rms

Yes

It injects common noise into the link. You can specify the location of the noise injection either after the package or after the die.

Click Jitter/Noise Options to further configure each jitter and noise type. There are two jitter/noise modes for Intel® Advanced Link Analyzer’s transmitters: Jitter/Noise Component mode and DJ/RJ-DN/RJ mode. Only one jitter/noise mode is active at a time, and you must determine which mode to use in your simulations. Refer to Characterization Data Access for usage and meaning of Linked to Characterization Data check box in the Jitter/Noise panel.

  • Jitter/Noise Component mode— Intel® Advanced Link Analyzer uses a flat jitter/noise structure that assumes no overlapping among all the jitter and noise components. Avoid double counting when inputting or importing jitter/noise figures. The following figure shows six specific jitter components: DCD, ISI, SJ, BUJ, RJ, and jitter PDF. The noise components DN, BUN, RN, and noise PDF must also be specified separately.
    Figure 20. Specifying Transmitter Jitter and Noise in Jitter/Noise Mode
    Specifying Transmitter Jitter and Noise in DJ/RJ-DN/RN
    Figure 21. Transmitter Jitter/Noise Configuration in Jitter/Noise Component Mode
  • DJ/RJ-DN/RJ mode—All deterministic jitter/noise components are included in DJ and DN.
    Figure 22. Specifying Transmitter Jitter and Noise in DJ/RJ-DN/RJ Mode
    Specifying Transmitter Jitter and Noise in DJ/RJ-DN/RJ Mode
    Figure 23. Transmitter Jitter/Noise Configuration in DJ/RJ-DN/RJ Method
  • Clock Jitter/Noise—Clock path transmitter uses the same jitter/noise configuration method as the data path transmitter’s jitter/noise component mode.
    Figure 24. Specifying Clock Path Transmitter Jitter/Noise
Figure 25. Clock Path Transmitter Jitter/Noise Configuration
Note: Jitter specified in the Transmitter Noise/Jitter panel is the transmitter’s intrinsic jitter and noise. Jitter specified in the Reference Clock configuration window is the external reference clock jitter. You must distinguish between these two parts and avoid double-counting jitter from the same source.
Level Two Title