Intel® FPGA Power and Thermal Calculator User Guide

ID 683445
Date 3/31/2023
Public

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5.14. Intel® FPGA PTC - HBM Page

The HBM data entry page of the Intel® FPGA Power and Thermal Calculator (PTC) shows the power information pertaining to high-bandwidth memory (HBM). This page is available for Intel® Agilex™ 7 M-series and Intel® Stratix® 10 devices only.
Table 27.  HBM Channel Configuration
Column Heading   Description
Entity Name   A user-editable field to name each entity of the design.
Full Hierarchy Name   Specify the hierarchical path relevant to this entry. This is an optional entry. When entering levels of hierarchy, the pipe character (|) denotes a level of hierarchy.
HBM ID   Select the top or bottom HBM stack in devices that include multiple stacks.
Channel ID   Selects a particular die in the stack.
PC0 Traffic Pattern   Select the traffic pattern that most closely matches your application. (PC0 and PC1 refer to the two pseudo-channels that each physical channel [0-7] is divided into; you can select different traffic patterns for each pseudo-channel.) Intel Stratix 10 devices only.
PC1 Traffic Pattern   Select the traffic pattern that most closely matches your application. (PC0 and PC1 refer to the two pseudo-channels that each physical channel [0-7] is divided into; you can select different traffic patterns for each pseudo-channel.) Intel Stratix 10 devices only.
Pseudo channel 0 Read Rate % Select to most closely match your application. Intel® Agilex™ 7 M-series devices only.
Bandwidth %
Page Hit Rate %
Pseudo channel 1 Read Rate % Select to most closely match your application. Intel® Agilex™ 7 M-series devices only.
Bandwidth %
Page Hit Rate %
User Comment   User Comment field.
Figure 41. HBM Page of the Intel® FPGA PTC ( Intel® Stratix® 10 Devices)


Figure 42. HBM Page of the Intel® FPGA PTC ( Intel® Agilex™ 7 M-series Devices)