40Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683436
Date 4/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Overview 3. Running the Design Example Tests 4. Using the Design Example as a Platform for Further Evaluation 5. 40Gbps Ethernet AFU Design Example User Guide Archives 6. Document Revision History for 40Gbps Ethernet AFU Design Example User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronym List 1.4. Acceleration Glossary
2. Overview x
2.1. 40GbE Design Example AFU Hardware 2.2. 40GbE Design Example AFU Software
3. Running the Design Example Tests x
3.1. Setup Prerequisites 3.2. Running 40GbE Internal Loopback Test in Single Intel® PAC System 3.3. Running 40GbE External Loopback Test in Single Intel® PAC System 3.4. Running 40GbE Intel® PAC-to-PAC Test between two connected Intel® PACs
4. Using the Design Example as a Platform for Further Evaluation x
4.1. Prerequisite while Evaluating with the Intel FPGA MAC/PHY IP 4.2. Evaluation with an Alternate MAC/PHY IP
1. About this Document
2. Overview
3. Running the Design Example Tests
4. Using the Design Example as a Platform for Further Evaluation
5. 40Gbps Ethernet AFU Design Example User Guide Archives
6. Document Revision History for 40Gbps Ethernet AFU Design Example User Guide

3.1. Setup Prerequisites

To install the Intel® PAC and OPAE SDK on a supported platform, follow the Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA. If you only want to evaluate network port operation using the pre-compiled AFs from the OPAE SDK installation, you do not need the Intel® Quartus® Prime Pro Edition software.

The OPAE_PLATFORM_ROOT environment variable points to the location where you installed the OPAE SDK, which is delivered as part of the Acceleration Stack for Intel® PAC with Intel® Arria® 10 GX FPGA.

In a multi-card system, use the following command to find the device sysfs entry associated with the desired PCIe device: 
$ ls -lrt /sys/class/fpga/intel-fpga-dev.*/
Sample output: 
/sys/class/fpga/intel-fpga-dev.1/:

total 0

-rw-r--r--.  1 root root 4096 Apr  7 21:46 uevent

drwxr-xr-x.  4 root root    0 Apr  7 21:46 intel-fpga-port.1

drwxr-xr-x. 12 root root    0 Apr  7 21:46 intel-fpga-fme.1

lrwxrwxrwx.  1 root root    0 Apr  7 21:46 subsystem -> ../../../../../../class/fpga

drwxr-xr-x.  2 root root    0 Apr  7 21:46 power

lrwxrwxrwx.  1 root root    0 Apr  7 21:49 device -> ../../../0000:af:00.0



/sys/class/fpga/intel-fpga-dev.0/:

total 0

lrwxrwxrwx.  1 root root    0 Apr  7 21:46 subsystem -> ../../../../../../class/fpga

lrwxrwxrwx.  1 root root    0 Apr  7 21:49 device -> ../../../0000:86:00.0

drwxr-xr-x. 12 root root    0 Apr  7 23:27 intel-fpga-fme.0

-rw-r--r--.  1 root root 4096 Apr  7 23:27 uevent

drwxr-xr-x.  2 root root    0 Apr  7 23:27 power

drwxr-xr-x.  4 root root    0 Apr  7 23:27 intel-fpga-port.0
This shows that the dev1 PCIe B:D.F is af:00.0 and dev0 PCIe B:D.F is 86:00.0.
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