2.1. 40GbE Design Example AFU Hardware
The design example uses the Intel FPGA 40G Ethernet MAC and PHY IP core to send and receive 40GbE ethernet packets on the Intel® PAC’s QSFP+ network port. The design example supports generating and checking all network traffic data on the Intel® PAC only through the implemented traffic generation and checking module in the AFU.
- The MAC IP instance connects to the HSSI PHY using the HSSI device class interface defined by OPAE. For more information about HSSI interface and 40G Ethernet MAC and PHY IP core connection, refer to the HSSI User Guide for Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA.
- The HSSI PHY implemented in the FIM connects to the FPGA’s transceiver I/O.
The HSSI Controller in the FIM utilizes transceiver reconfiguration to set the desired mode of the HSSI PHY. The design example requires that the host set the HSSI PHY mode to 40GBASE-SR4 (PMA only) .
The design example utilizes the PR Management Interface ports on the hssi interface for internal purpose. Intel recommends you to terminate these ports in your AFU designs, refer to the HSSI User Guide for Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA for more details.
Note: The Intel® Acceleration Stack version 1.1 supports PHY modes of 4x10GBASE-SR (PCS/PMA) and 40GBASE-SR4 (PMA only).
Use OPAE tools and APIs from the host to initialize and control packet transfers, and collect port statistics.