10Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683422
Date 4/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Overview 3. Running the Design Example Tests 4. Using the Design Example as a Platform for Further Evaluation 5. 10Gbps Ethernet AFU Design Example User Guide Archives A. Document Revision History for 10Gbps Ethernet AFU Design Example User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronym List 1.4. Acceleration Glossary
2. Overview x
2.1. 10GbE Design Example AFU Hardware 2.2. 10GbE Design Example AFU Software
3. Running the Design Example Tests x
3.1. Setup Prerequisites 3.2. Running 10GbE Internal Loopback Test in Single Intel® PAC System 3.3. Running 10GbE External Loopback Test in Single Intel® PAC System 3.4. Running 10GbE Intel® PAC-to-PAC Test between two connected Intel® PACs
4. Using the Design Example as a Platform for Further Evaluation x
4.1. Prerequisite while Evaluating with the Intel FPGA MAC IP 4.2. Evaluation with an Alternate MAC IP
1. About this Document
2. Overview
3. Running the Design Example Tests
4. Using the Design Example as a Platform for Further Evaluation
5. 10Gbps Ethernet AFU Design Example User Guide Archives
A. Document Revision History for 10Gbps Ethernet AFU Design Example User Guide

1. About this Document

Updated for:
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.2

This document provides an overview of the 10Gbps Ethernet Accelerator Functional Unit (AFU) design example included in the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs and instructions to quickly evaluate the network port capability of the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA.

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