AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

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ID 683421
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. DAC3XJ8XEVM Software Setup 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and DAC37J84 Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 719 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Transmitter Data Link Layer 1.4.2. Transmitter Transport Layer 1.4.3. Scrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Transmitter Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Lane Alignment Sequence (ILAS)
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

1.5. JESD204B IP Core and DAC37J84 Configurations

The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the DAC37J84 device and Quick Start tab of DAC3XJ8XEVM GUI. The transceiver data rate, device clock frequency, and other JESD204B parameters comply with the DAC37J84 operating conditions.

The hardware checkout testing implements the JESD204B IP core with the following parameter configuration.

Table 6.   Parameter Configuration

Configuration

Setting

Setting

Setting

Setting

LMF

148

244

442

841

HD

0

0

0

1

S

1

1

1

1

N

16

16

16

16

N’

16

16

16

16

CS

0

0

0

0

CF

0

0

0

0

Subclass

1

1

1

1

DAC Interpolation

8

4

2

1

DAC Device Clock (MHz)

983.04

1228.8

1228.8

1228.8

DAC Data Input Rate (MSPS)

122.88

307.2

614.4

1228.8

FPGA Device Clock (MHz) 6

245.76

307.2

307.2

307.2

FPGA Management Clock (MHz)

100

100

100

100

FPGA Frame Clock (MHz) 7

122.88

307.2

307.2

307.2

FPGA Link Clock (MHz) 7

245.76

307.2

307.2

307.2

FPGA TX PHY Mode 8

Bonded

Bonded

Bonded

Non-bonded

PCS Option9

Hard PCS

Soft PCS

Soft PCS

Soft PCS

Character Replacement

Enabled

Enabled

Enabled

Enabled

Test Data Pattern

  • (0xF1, 0xE2, 0xD3, 0xC4, 0xB5, 0xA6, 0x97, 0x80) 10
  • Sine 11
  • Single pulse 12
  • (0xF1, 0xE2,0xD3, 0xC4) 10
  • Sine 11
  • Single pulse 12
  • (0xF1, 0xE2) 10
  • Sine 11
  • Single pulse 12
  • (0xF1) 10
  • Sine 11
  • Single pulse 12
6 The device clock is used to clock the transceiver.
7 The FPGA frame clock and link clock for LMF=244, 442, and 841 modes are sourced directly from the FPGA device clock (LMK04828 clock channel CLKout0). For LMF=148 mode, the link clock is sourced directly from the FPGA device clock, while the frame clock is sourced from the LMK04828 clock channel CLKout12 through the FMC connector.
8 The ATX PLL is used in the JESD204B IP core. The TX PHY mode selected is compatible with the transceiver channel placement rules in the Quartus II software.
9 A data rate beyond 12200 Mbps requires a soft PCS to be enabled in the JESD204B IP core.
10 Each frame clock cycle consists of the test pattern in parentheses. Refer to JESD204B specification section 5.1.6.2 for short transport layer test pattern definition.
11 Sine wave pattern is used in TL.2 and SCR.2 test cases to verify that pattern generated in the FPGA transport layer is transmitted by DAC analog channel.
12 Single pulse pattern is used in deterministic latency measurement test cases DL.1 and DL.2 only.
Level Two Title