AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

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ID 683421
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. DAC3XJ8XEVM Software Setup 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and DAC37J84 Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 719 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Transmitter Data Link Layer 1.4.2. Transmitter Transport Layer 1.4.3. Scrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Transmitter Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Lane Alignment Sequence (ILAS)
1. Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report

1.1. Hardware Requirements

The hardware checkout test requires the following hardware and software tools:

  • Altera Stratix V Advanced Systems Development Kit with 15 V power adaptor
  • HSMC breakout board included in the Stratix V Advanced Systems Development Kit
  • TI DAC37J84 EVM with 5.0 V power adaptor
  • Mini-USB cables
  • SMA cables
  • Wire for connecting J21 header to HSMC breakout board header
  • Oscilloscope with a minimum bandwidth of 4 GHz
Level Two Title