| 2023.11.09 |
23.1 |
20.2.3 |
- Added the following subtopics under Constraining the I/O Pins section:
- General Purpose I/O
- Dedicated Active Serial Interface
|
| 2023.10.11 |
23.1 |
20.2.3 |
- Edited table Ports Description:
- Removed Interrupt.
- Updated Conduit Interface.
- Added ASMI Block Interface.
|
| 2023.04.10 |
23.1 |
20.2.3 |
- Updated product family name to " Intel Agilex® 7".
- Edited Device Family Support to replace Intel Agilex® with " Intel Agilex® 7" devices and added clarity to the footnotes.
- Edited the footnotes in the table Ports Description to improve clarity.
|
| 2022.12.22 |
22.2 |
20.2.1 |
- Added a note in Table: Ports Description to state that only one port (avl_csr or avl_mem) can be accessed at a time.
- Made minor editorial edits.
|
| 2022.07.25 |
22.2 |
20.2.1 |
- Updated Intel HAL Driver topic:
- Added a note for Flash_Timeout.
- Added a note to state support for Intel® Quartus® Prime Pro Edition software only.
- Added ETIME error code in intel_gsfi_erase_block, intel_gsfi_write_block, intel_gsfi_write, intel_gsfi_lock in Driver API topic.
|
| 2022.06.23 |
22.2 |
20.2.1 |
- Updated Parameter Settings - General tab in Parameters section.
- Added Parameter Settings - Simulation tab table in Parameters section.
- Updated title Nios II HAL Driver to Intel HAL Driver.
- Updated instances of Nios II to Intel in Intel HAL Driver section.
- Added support for QSPI flash device in Intel HAL Driver section.
- Added note in Intel HAL Driver section.
- Added related information for Nios V Configuration and Booting Solutions in Intel HAL Driver section.
- Updated Prototype, Return, Description in intel_gsfi_get_info, intel_gsfi_read, intel_gsfi_erase_block, intel_gsfi_write_block, intel_gsfi_write in Intel HAL Driver section.
- Added intel_gsfi_lock, intel_gsfi_chip_select, and intel_gsfi_config tables in Intel HAL Driver section.
|
| 2022.04.20 |
22.1 |
20.1.1 |
Corrected the Reserved Bit value for the following registers in Table: Register Map:
- From 31:8 to 31:9 for Control Register.
- From 31:14 to 31:13 for Read Instruction Register.
|
| 2022.04.07 |
22.1 |
20.1.1 |
Updated description for Flash Access Using the Generic Serial Flash Interface Intel FPGA IP section with additional information. |
| 2021.11.09 |
21.2 |
20.1.1 |
Updated CS Delay Setting Register in Register Map topic. |
| 2021.06.21 |
21.2 |
20.1.1 |
- Updated Device Family Support.
- Updated Nios® II HAL Driver:
- Updated the intel_gsfi_get_info description in Table: intel_gsfi_get_info.
- Updated the intel_gsfi_read description in Table: intel_gsfi_read.
- Nios® II HAL Driver
- Removed the Driver API Application topic.
- Updated Figure: Reference Design Block Diagram.
|
| 2021.03.29 |
21.1 |
20.1.1 |
- Added the following sections:
- Nios II HAL Drivers
- Driver API
- Driver API Application
- Corrected the default value for dummy cycles from 0xA to 0x0 in Table: Register Map.
- Updated the steps in the Perform Page Program (Extended Mode) and Perform 4-byte Quad Input Fast Program (Quad SPI Mode) examples in Program Flash.
|
| 2020.09.28 |
20.3 |
20.0.0 |
- Added a new register setting—tSHSL.
- Added a new section—Constraining the I/O Pins.
- Updated the description for Enable flash simulation model in Table: Parameter Settings.
- Removed Control Status Register Operations.
- Updated the following topics:
- Generic Serial Flash Interface Intel® FPGA IP User Guide
- Release Information
- Memory Operations
- Updated the Hardware and Software Requirements of the Generic Serial Flash Interface Intel® FPGA IP Reference Design section.
- Updated the description of On-Chip Memory Intel® FPGA IP in Table: Reference Design Components Descriptions.
- Updated Creating Nios® II Hardware System:
- Updated the description in step 7c.
- Updated Figure: Completed Platform Designer Connection.
- Made minor editorial updates through out the document.
|
| 2020.05.08 |
20.1 |
19.2.1 |
- Added new sections—Release Information and Control Status Register Byte Enable.
- Updated Table: Parameter Settings to include a new parameter—Use byteenable for CSR.
- Added a new signal—avl_csr_byteenable.
- Updated Figure: Signal Block Diagram.
- Updated the note to the Device Family Support topic.
|
| 2020.04.13 |
19.4 |
19.1.1 |
- Renamed document title as Generic Serial Flash Interface Intel® FPGA IP User Guide
- Added the Byte Enabling section.
- Added a note to the Device Family Support topic.
- Updated the Memory Operations topic.
- Updated for latest branding standards.
|
| 2019.11.27 |
19.3 |
19.1 |
Added a note to the Memory Operations topic. |
| 2019.09.30 |
19.3 |
19.1 |
- Added support for Intel® Agilex™ devices.
- Updated the Device Family Support topic.
- Made minor editorial updates to the document.
|
| 2018.11.09 |
18.1 |
18.1 |
- Added the Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP Core section.
- Added the Generic Serial Flash Interface Intel® FPGA IP Core User Guide Archives section.
- Updated the Generic Serial Flash Interface Intel® FPGA IP Core User Guide section to provide more information on the Generic Serial Flash Interface Intel® FPGA IP core.
- Updated the signal names of the Signal Block Diagram figure.
- Updated the Conduit Interface signal names in the Ports Description table.
- Updated the description of the write opcode field name of the write instruction register in the Register Map table.
|
| 2018.05.16 |
18.0 |
18.0 |
- Updated the Generic Serial Flash Interface Intel FPGA IP Core Reference Design Files link.
- Added Flash Command Address Register in the Register Map.
|
| 2018.05.07 |
18.0 |
18.0 |
Initial release. |