2.4.1. Power-Up Sequence Requirements for Stratix® 10 Devices
The power rails in Stratix® 10 devices are each divided into three groups. Refer to the Stratix® 10 Device Family Pin Connection Guidelines and AN692: Power Sequencing Considerations for Cyclone® 10 GX, Arria® 10, and Stratix® 10 Devices for additional details.
The diagram below illustrates the voltage groups of the Stratix® 10 devices and their required power-up sequence.
Power Group | Stratix® 10 GX and SX (L-Tile and H-Tile) | Stratix® 10 MX (HBM, H-Tile, and E-Tile) | Stratix® 10 TX (H-Tile and E-Tile) | Stratix® 10 DX (E-Tile and P-Tile) |
---|---|---|---|---|
Group 1 | VCC VCCP VCCERAM VCCR_GXB VCCT_GXB VCCL_HPS VCCPLLDIG_SDM VCCPLLDIG_HPS |
VCC VCCP VCCERAM VCCR_GXB VCCT_GXB VCCPLLDIG_SDM VCCRT_GXE VCCRTPLL_GXE |
VCC VCCP VCCERAM VCCR_GXB VCCT_GXB VCCL_HPS VCCPLLDIG_SDM VCCPLLDIG_HPS VCCRT_GXE VCCRTPLL_GXE |
VCC VCCP VCCERAM VCCFUSE_GXP 12 VCCRT_GXP VCCL_HPS VCCPLLDIG_SDM VCCPLLDIG_HPS VCCRT_GXE VCCRTPLL_GXE |
Group 2 | VCCPT VCCH_GXB VCCA_PLL VCCPLL_HPS VCCPLL_SDM VCCADC |
VCCPT VCCH_GXB VCCA_PLL VCCPLL_SDM VCCADC VCCM_WORD 13 VCCH_GXE VCCCLK_GXE |
VCCPT VCCH_GXB VCCA_PLL VCCPLL_HPS VCCPLL_SDM VCCADC VCCH_GXE VCCCLK_GXE |
VCCPT VCCA_PLL VCCPLL_HPS VCCPLL_SDM VCCADC VCCM_WORD 13 VCCH_GXP VCCCLK_GXP VCCH_GXE VCCCLK_GXE |
Group 3 | VCCIO 14 VCCIO3V 14 VCCIO_SDM 14 VCCIO_HPS 14 VCCFUSEWR_SDM VCCIO3D 15 |
VCCIO VCCIO3V VCCIO_SDM VCCIO_UIB 13 VCCFUSEWR_SDM |
VCCIO VCCIO3V VCCIO_SDM VCCIO_HPS VCCFUSEWR_SDM |
VCCIO VCCIO_SDM VCCIO_HPS VCCIO_UIB 13 VCCFUSEWR_SDM |
Group 4 | VCCIO3C 15 |
— | — | — |
All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their respective nominal voltage before the power rails from Group 2 can start ramping up.
The power rails within Group 2 can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2 must ramp to a minimum threshold of 90% of their nominal value before the Group 3 power rails can start ramping up.
The power rails within Group 3 can ramp up in any order after the last power rail in Group 2 ramps up to a minimum threshold of 90% of their full value.
Group 4 power rails can ramp up after the last power rail in Group 3 ramps up to a minimum threshold of 90% of their full value.
All power rails must ramp up monotonically. The power-up sequence should meet either the standard or the fast POR delay time. The POR delay time depends on the POR delay setting you use. For the POR specifications of the Stratix® 10 devices, refer to the POR Specifications section in the Stratix® 10 Device Datasheet .
For configuration via protocol (CvP), the total tRAMP must be less than 10 ms from the first power supply ramp-up to the last power supply ramp-up. Select a fast POR delay setting to allow sufficient time for the PCI Express* ( PCIe* ) link initialization and configuration. For more details about power supply ramp up for the CvP mode, refer to the Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide.