External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide

Download PDF
ID 683408
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP 2. Design Example Description for External Memory Interfaces Intel® Stratix® 10 FPGA IP 3. Document Revision History for External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP x
1.1. Creating an EMIF Project 1.2. Generating and Configuring the EMIF IP 1.3. Generating the Synthesizable EMIF Design Example 1.4. Generating the EMIF Design Example for Simulation 1.5. Simulation Versus Hardware Implementation 1.6. Simulating External Memory Interface IP With ModelSim 1.7. Pin Placement for Intel® Stratix® 10 EMIF IP 1.8. Compiling and Programming the Intel® Stratix® 10 EMIF Design Example 1.9. Debugging the Intel® Stratix® 10 EMIF Design Example
1.2. Generating and Configuring the EMIF IP x
1.2.1. Intel® Stratix® 10 EMIF Parameter Editor Guidelines
2. Design Example Description for External Memory Interfaces Intel® Stratix® 10 FPGA IP x
2.1. Synthesis Example Design 2.2. Simulation Example Design 2.3. Example Designs Interface Tab
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP
2. Design Example Description for External Memory Interfaces Intel® Stratix® 10 FPGA IP
3. Document Revision History for External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide

1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 21.1
IP Version 19.2.3
A new interface and more automated design example flow is available for Intel® Stratix® 10 external memory interfaces.

The Example Designs tab in the parameter editor allows you to specify the creation of synthesis and simulation file sets which you can use to validate your EMIF IP.

You can generate an example design specifically for an Intel FPGA development kit, or for any EMIF IP that you generate.

Figure 1. General Design Example Workflows
Figure 2. Generating an EMIF Example Design With an Intel® Stratix® 10 Development Kit


Section Content
Creating an EMIF Project
Generating and Configuring the EMIF IP
Generating the Synthesizable EMIF Design Example
Generating the EMIF Design Example for Simulation
Simulation Versus Hardware Implementation
Simulating External Memory Interface IP With ModelSim
Pin Placement for Intel Stratix 10 EMIF IP
Compiling and Programming the Intel Stratix 10 EMIF Design Example
Debugging the Intel Stratix 10 EMIF Design Example

Level Two Title