External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683408
Date 3/29/2021
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Document Table of Contents
Document Table of Contents x
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP 2. Design Example Description for External Memory Interfaces Intel® Stratix® 10 FPGA IP 3. Document Revision History for External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP x
1.1. Creating an EMIF Project 1.2. Generating and Configuring the EMIF IP 1.3. Generating the Synthesizable EMIF Design Example 1.4. Generating the EMIF Design Example for Simulation 1.5. Simulation Versus Hardware Implementation 1.6. Simulating External Memory Interface IP With ModelSim 1.7. Pin Placement for Intel® Stratix® 10 EMIF IP 1.8. Compiling and Programming the Intel® Stratix® 10 EMIF Design Example 1.9. Debugging the Intel® Stratix® 10 EMIF Design Example
1.2. Generating and Configuring the EMIF IP x
1.2.1. Intel® Stratix® 10 EMIF Parameter Editor Guidelines
2. Design Example Description for External Memory Interfaces Intel® Stratix® 10 FPGA IP x
2.1. Synthesis Example Design 2.2. Simulation Example Design 2.3. Example Designs Interface Tab
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP
2. Design Example Description for External Memory Interfaces Intel® Stratix® 10 FPGA IP
3. Document Revision History for External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide

1.5. Simulation Versus Hardware Implementation

For external memory interface simulation, you can select either skip calibration or full calibration on the Diagnostics tab during IP generation.

EMIF Simulation Models

This table compares the characteristics of the skip calibration and full calibration models.

Table 2.  EMIF Simulation Models: Skip Calibration versus Full Calibration
Skip Calibration Full Calibration
System-level simulation focusing on user logic. Memory interface simulation focusing on calibration.
Details of calibration are not captured. Captures all stages of calibration.
Has ability to store and retrieve data. Includes leveling, per-bit deskew, etc.
Represents accurate efficiency.
Does not consider board skew.

RTL Simulation Versus Hardware Implementation

This table highlights key differences between EMIF simulation and hardware implementation.

Table 3.  EMIF RTL Simulation Versus Hardware Implementation
RTL Simulation Hardware Implementation
Nios® initialization and calibration code execute in parallel. Nios® initialization and calibration code execute sequentially.
Interfaces assert cal_done signal signal simultaneously in simulation. Fitter operations determine the order of calibration, and interfaces do not assert cal_done simultaneously.

You should run RTL simulations based on traffic patterns for your design's application. Note that RTL simulation does not model PCB trace delays which may cause a discrepancy in latency between RTL simulation and hardware implementation.

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