AN 861: Intel® Stratix® 10 H-Tile PCI Express* Link Hardware Validation

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ID 683407
Date 6/29/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 H-Tile PCIe* Link Hardware Validation
1. Intel® Stratix® 10 H-Tile PCIe* Link Hardware Validation x
1.1. Overview 1.2. Hardware Validation System Block Diagram 1.3. Hardware and Software Requirements 1.4. Quick Start Guide 1.5. Document Revision History
1.3. Hardware and Software Requirements x
1.3.1. Hardware Requirements 1.3.2. Software Requirements
1.4. Quick Start Guide x
1.4.1. Hardware Setup 1.4.2. Running the Reference Design 1.4.3. Hardware Validation
1.4.2. Running the Reference Design x
1.4.2.1. Generating the Design 1.4.2.2. Compiling the Design Example and Programming the Device
1.4.3. Hardware Validation x
1.4.3.1. Hardware Validation on the Linux Platform 1.4.3.2. Hardware Validation on the Windows Platform
1.4.3.1. Hardware Validation on the Linux Platform x
1.4.3.1.1. Linux Kernel Driver 1.4.3.1.2. Installing the Linux Kernel Driver 1.4.3.1.3. Running the Design Example Application
1.4.3.2. Hardware Validation on the Windows Platform x
1.4.3.2.1. Installing the Windows driver 1.4.3.2.2. Running the Windows demo driver with design example
1. Intel® Stratix® 10 H-Tile PCIe* Link Hardware Validation

1.2. Hardware Validation System Block Diagram

Figure 1. Hardware Validation System Simplified Block Diagram

The figure above shows the simplified block diagram of the hardware validation system. The Root Port in this system is the host PC, which interfaces with the PIO design example to perform memory reads and memory writes on an on-chip memory without the use of DMA.

The three main components of the design example are:

  1. Device-Under-Test (DUT): This refers to the PCIe* Hard IP (HIP), which you can configure.
  2. PIO Application: This takes in the Avalon® -ST data and converts it to the Avalon® -MM format before sending it to the slave.
  3. The slave in this case is an on-chip memory with a size that matches the DUT's BAR size.

For the host (or Root Port), a driver and application software are provided for the validation process. After the driver is installed, the hardware will be initialized and ready for transactions. Data is then packetized, and can be received by the DUT. In the validation process, the application software performs Memory Writes to the on-chip memory followed by Memory Reads from the on-chip memory. It then compares the written data with the read data. A matching dataset indicates a successful validation.

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