Intel® FPGA SDK for OpenCL™ Standard Edition: Custom Platform Toolkit User Guide

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ID 683398
Date 9/24/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide 2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide x
1.1. Prerequisites for the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit 1.2. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.3. Custom Platform Automigration for Forward Compatibility 1.4. Creating an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.5. Applying for the Intel® FPGA SDK for OpenCL™ Standard Edition Preferred Board Status 1.6. Shipping Recommendations 1.7. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Design Revision History
1.2. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform x
1.2.1. Directories and Files in an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.2.2. Recommendations for Structuring the Custom Platform Directory
1.3. Custom Platform Automigration for Forward Compatibility x
1.3.1. Customizing Automigration
1.4. Creating an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform x
1.4.1. Designing the Board Hardware 1.4.2. Creating the Board XML Files 1.4.3. Creating the MMD Library 1.4.4. Setting Up the FPGA Client Driver 1.4.5. Providing Intel® FPGA SDK for OpenCL™ Standard Edition Utilities Support 1.4.6. Testing the Hardware Design
1.4.1. Designing the Board Hardware x
1.4.1.1. Creating the Board Platform Designer (Standard) System 1.4.1.2. Establishing Guaranteed Timing Flow
1.4.1.1. Creating the Board Platform Designer (Standard) System x
1.4.1.1.1. General Quality of Results Considerations for the Exported Board Partition
1.4.2. Creating the Board XML Files x
1.4.2.1. Creating the board_env.xml File 1.4.2.2. Creating the board_spec.xml File
1.4.2.1. Creating the board_env.xml File x
1.4.2.1.1. Testing the board_env.xml File
1.4.3. Creating the MMD Library x
1.4.3.1. Kernel Power-up State
2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material x
2.1. The Board Platform Designer (Standard) Subsystem 2.2. XML Elements, Attributes, and Parameters in the board_spec.xml File 2.3. MMD API Descriptions 2.4. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Manual Revision History
2.1. The Board Platform Designer (Standard) Subsystem x
2.1.1. Intel® FPGA SDK for OpenCL™ Standard Edition-Specific Platform Designer (Standard) System Components
2.1.1. Intel® FPGA SDK for OpenCL™ Standard Edition-Specific Platform Designer (Standard) System Components x
2.1.1.1. OpenCL Kernel Clock Generator 2.1.1.2. OpenCL Kernel Interface 2.1.1.3. OpenCL Memory Bank Divider
2.2. XML Elements, Attributes, and Parameters in the board_spec.xml File x
2.2.1. board 2.2.2. device 2.2.3. global_mem 2.2.4. host 2.2.5. channels 2.2.6. interfaces 2.2.7. interface 2.2.8. compile
2.3. MMD API Descriptions x
2.3.1. aocl_mmd_get_offline_info 2.3.2. aocl_mmd_get_info 2.3.3. aocl_mmd_open 2.3.4. aocl_mmd_close 2.3.5. aocl_mmd_read 2.3.6. aocl_mmd_write 2.3.7. aocl_mmd_copy 2.3.8. aocl_mmd_set_interrupt_handler 2.3.9. aocl_mmd_set_status_handler 2.3.10. aocl_mmd_yield 2.3.11. aocl_mmd_shared_mem_alloc 2.3.12. aocl_mmd_shared_mem_free 2.3.13. aocl_mmd_reprogram 2.3.14. aocl_mmd_hostchannel_create 2.3.15. aocl_mmd_hostchannel_destroy 2.3.16. aocl_mmd_hostchannel_get_buffer 2.3.17. aocl_mmd_hostchannel_ack_buffer
2.3.13. aocl_mmd_reprogram x
2.3.13.1. Reprogram Support
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide
2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material

2.1.1.1. OpenCL Kernel Clock Generator

The OpenCL™ Kernel Clock Generator is a Platform Designer (Standard) component that generates a clock output and a clock 2x output for use by the OpenCL kernels. An Avalon®-MM slave interface allows reprogramming of the phase-locked loops (PLLs) and kernel clock status information.
Table 5.  Parameter Settings for the OpenCL Kernel Clock Generator Component
Parameter Description
REF_CLK_RATE Frequency of the reference clock that drives the kernel PLL (that is, pll_refclk).
KERNEL_TARGET_CLOCK_RATE Frequency that the Intel® Quartus® Prime Standard Edition software attempts to achieve during compilation.

Keep this parameter at its default setting.

Table 6.  Signals and Ports for the OpenCL Kernel Clock Generator Component
Signal or Port Description
pll_refclk The reference clock for the kernel PLL. The frequency of this clock must match the frequency you specify for the REF_CLK_RATE component parameter.
clk The clock used for the host control interface. The clock rate of clk can be slow.
reset The reset signal that resets the PLL and the control logic. Resetting the PLL disables the kernel clocks temporarily. Connect this reset signal to the power-on reset signal in your system.
ctrl The slave port used to connect to the OpenCL host interface and to adjust the frequency based on the OpenCL kernel.
kernel_clk

kernel_clk2x

The kernel clock and its 2x variant that runs on twice the speed. The kernel_clk2x signal is directly exported from this interface. Because kernel_clk has internal Platform Designer (Standard) connections, export it using a clock source component. You can also use the clock source to export the kernel reset. In addition, clock all logic at the board Platform Designer (Standard) system interface with kernel_clk, except for any I/O that you add.
kernel_pll_locked (Optional) If the PLL is locked onto the reference clock, the value of this signal is 1. The host interface manages this signal normally; however, this signal is made available in the board Platform Designer (Standard) system.
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