Intel® FPGA SDK for OpenCL™ Standard Edition: Custom Platform Toolkit User Guide

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ID 683398
Date 9/24/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide 2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide x
1.1. Prerequisites for the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit 1.2. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.3. Custom Platform Automigration for Forward Compatibility 1.4. Creating an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.5. Applying for the Intel® FPGA SDK for OpenCL™ Standard Edition Preferred Board Status 1.6. Shipping Recommendations 1.7. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Design Revision History
1.2. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform x
1.2.1. Directories and Files in an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.2.2. Recommendations for Structuring the Custom Platform Directory
1.3. Custom Platform Automigration for Forward Compatibility x
1.3.1. Customizing Automigration
1.4. Creating an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform x
1.4.1. Designing the Board Hardware 1.4.2. Creating the Board XML Files 1.4.3. Creating the MMD Library 1.4.4. Setting Up the FPGA Client Driver 1.4.5. Providing Intel® FPGA SDK for OpenCL™ Standard Edition Utilities Support 1.4.6. Testing the Hardware Design
1.4.1. Designing the Board Hardware x
1.4.1.1. Creating the Board Platform Designer (Standard) System 1.4.1.2. Establishing Guaranteed Timing Flow
1.4.1.1. Creating the Board Platform Designer (Standard) System x
1.4.1.1.1. General Quality of Results Considerations for the Exported Board Partition
1.4.2. Creating the Board XML Files x
1.4.2.1. Creating the board_env.xml File 1.4.2.2. Creating the board_spec.xml File
1.4.2.1. Creating the board_env.xml File x
1.4.2.1.1. Testing the board_env.xml File
1.4.3. Creating the MMD Library x
1.4.3.1. Kernel Power-up State
2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material x
2.1. The Board Platform Designer (Standard) Subsystem 2.2. XML Elements, Attributes, and Parameters in the board_spec.xml File 2.3. MMD API Descriptions 2.4. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Manual Revision History
2.1. The Board Platform Designer (Standard) Subsystem x
2.1.1. Intel® FPGA SDK for OpenCL™ Standard Edition-Specific Platform Designer (Standard) System Components
2.1.1. Intel® FPGA SDK for OpenCL™ Standard Edition-Specific Platform Designer (Standard) System Components x
2.1.1.1. OpenCL Kernel Clock Generator 2.1.1.2. OpenCL Kernel Interface 2.1.1.3. OpenCL Memory Bank Divider
2.2. XML Elements, Attributes, and Parameters in the board_spec.xml File x
2.2.1. board 2.2.2. device 2.2.3. global_mem 2.2.4. host 2.2.5. channels 2.2.6. interfaces 2.2.7. interface 2.2.8. compile
2.3. MMD API Descriptions x
2.3.1. aocl_mmd_get_offline_info 2.3.2. aocl_mmd_get_info 2.3.3. aocl_mmd_open 2.3.4. aocl_mmd_close 2.3.5. aocl_mmd_read 2.3.6. aocl_mmd_write 2.3.7. aocl_mmd_copy 2.3.8. aocl_mmd_set_interrupt_handler 2.3.9. aocl_mmd_set_status_handler 2.3.10. aocl_mmd_yield 2.3.11. aocl_mmd_shared_mem_alloc 2.3.12. aocl_mmd_shared_mem_free 2.3.13. aocl_mmd_reprogram 2.3.14. aocl_mmd_hostchannel_create 2.3.15. aocl_mmd_hostchannel_destroy 2.3.16. aocl_mmd_hostchannel_get_buffer 2.3.17. aocl_mmd_hostchannel_ack_buffer
2.3.13. aocl_mmd_reprogram x
2.3.13.1. Reprogram Support
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide
2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material

2.1.1.3. OpenCL Memory Bank Divider

The OpenCL™ Memory Bank Divider is a Platform Designer (Standard) component that takes an incoming request from the host interface on the Avalon®-MM slave port and routes it to the appropriate bank master port. This component must reside on the path between the host and the global memory interfaces. In addition, it must reside outside of the path between the kernel and the global memory interfaces.
Table 9.  Parameter Settings for the OpenCL Memory Bank Divider Component
Parameter Description
Number of banks Number of memory banks for each of the global memory types included in your board system.
Separate read/write ports Enable this parameter so that each bank has one port for read operation and one for write operation.
Add pipeline stage to output Enable this parameter to allow for potential timing improvements.
Data Width Width of the data bus to the memory in bits.
Address Width (total addressable) Total number of address bits necessary to address all global memory.
Burst size (maximum) The maxburst value defined in the interface attribute of the global_mem element in the board_spec.xml file.
Maximum Pending Reads Maximum number of pending read transfers the component can process without asserting a waitrequest signal.
CAUTION:
A high Maximum Pending Reads value causes Platform Designer (Standard) to insert a deep response FIFO buffer, between the component's master and slave, that consumes a lot of device resources. It also increases the achievable bandwidth between host and memory interfaces.
Split read/write bursts on burst word boundary Enable splitting of read and write bursts on burst word boundary.

Enable this parameter if the Number of banks parameter value is greater than 1, and the burst reads and writes that the host controller sends to the slave port crosses burst word boundary.

Table 10.  Signals and Ports for the OpenCL Memory Bank Divider Component
Signal or Port Description
clk The bank divider logic uses this clock input. If the IP of your host and memory interfaces have different clocks, ensure that clk clock rate is not slower than the slowest of the two IP clocks.
reset The reset input that connects to the board power-on reset.
s The slave port that connects to the host interface controller.
kernel_clk The kernel_clk output from the OpenCL Kernel Clock Generator drives this clock input.
kernel_reset The kernel_reset output from the OpenCL Kernel Interface drives this reset input.
acl_bsp_snoop Export this Avalon® Streaming (Avalon-ST) source. In the board_spec.xml file, under interfaces, describe only the snoop interface for the default memory (acl_internal_snoop). If you have a heterogeneous memory design, perform these tasks only for the OpenCL Memory Bank Divider component associated with the default memory.
Important: The memory system you build in Platform Designer (Standard) alters the width of acl_bsp_snoop. You must update the width of the streamsource interface within the channels element in the board_spec.xml file to match the width of acl_bsp_snoop.
Important: In the board_spec.xml file, update the width of the snoop interface (acl_internal_snoop) specified with the streamsource kernel interface within the interfaces element. Updating the width ensures that the global_mem interface entries in board_spec.xml match the characteristics of the bank<N> Avalon-MM masters from corresponding OpenCL Memory Bank Divider component for the default memory.
acl_bsp_memorg_host This conduit connects to the acl_bsp_memorg_host interface of the OpenCL Kernel Interface.
bank1, bank2, ..., bank8 The number of memory masters available in the OpenCL Memory Bank Divider depends on the number of memory banks that were included when the unit was instantiated. Connect each bank with each memory interface in the same order as the starting address for the corresponding kernel memory interface specified in the board_spec.xml file.

For example, global_mem interface that begins at address 0 must correspond to the memory master in bank1 from the OpenCL Memory Bank Divider.

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