Visible to Intel only — GUID: cjb1542221175621
Ixiasoft
Unexpected AVST_READY Signal Behavior After Power-On-Reset (POR)
After powering up the FPGA device power supplies in the proper sequence, the device asserts a Power On Reset (POR). When you drive the nCONFIG pin high, subsequently the nSTATUS pin goes high. If you use either of the Avalon-ST configuration scheme(s) (32/16/8 bits), you may notice an unexpected low pulse (20 to 100 µs) on AVST_READY pin.
Figure 2. Timing Diagram
If you begin the configuration via Avalon-ST scheme by driving the AVST_VALID pin high before the unexpected AVST_READY low pulse (20 to 100 µs), then the configuration will be unsuccessful.
Note: This issue only impacts the first configuration after POR, it does not impact the subsequent reconfiguration attempts.
Workaround
After the nCONFIG and nSTATUS pins are high, wait for 500 µs before you monitor the AVST_READY pin and drive the AVST_VALID pin to initiate the Avalon-ST configuration.
Status
Affects:
- Intel® Stratix® 10 GX 2800 L-Tile devices
- Intel® Stratix® 10 GX 2500 L-Tile devices
Status: No planned fix.