FFT IP Core: User Guide

Download PDF
ID 683374
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. FFT IP Core Getting Started 3. FFT IP Core Functional Description 4. Block Floating Point Scaling 5. Document Revision History A. FFT IP Core User Guide Document Archive
1. About This IP Core x
1.1. Intel® DSP IP Core Features 1.2. FFT IP Core Features 1.3. General Description 1.4. DSP IP Core Device Family Support 1.5. DSP IP Core Verification 1.6. FFT IP Core Release Information 1.7. Performance and Resource Utilization
1.3. General Description x
1.3.1. Fixed Transform Size FFT 1.3.2. Variable Streaming FFT
2. FFT IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.5. Simulating Intel® FPGA IP Cores 2.6. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FFT IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.4. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) x
2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.5. Simulating Intel® FPGA IP Cores x
2.5.1. Simulating the Fixed-Transform FFT IP Core in the MATLAB Software 2.5.2. Simulating the Variable Streaming FFT IP Core in the MATLAB Software
3. FFT IP Core Functional Description x
3.1. Fixed Transform FFTs 3.2. Variable Streaming FFTs 3.3. FFT Processor Engines 3.4. I/O Data Flow 3.5. FFT IP Core Parameters 3.6. FFT IP Core Interfaces and Signals
3.2. Variable Streaming FFTs x
3.2.1. Fixed-Point Variable Streaming FFTs 3.2.2. Floating-Point Variable Streaming FFTs
3.3. FFT Processor Engines x
3.3.1. Quad-Output FFT Engine 3.3.2. Single-Output FFT Engine
3.4. I/O Data Flow x
3.4.1. Streaming FFT 3.4.2. Variable Streaming 3.4.3. Buffered Burst 3.4.4. Burst
3.4.1. Streaming FFT x
3.4.1.1. Using the Streaming FFT 3.4.1.2. Changing the Direction on a Block-by-Block Basis 3.4.1.3. Enabling the Streaming FFT
3.4.2. Variable Streaming x
3.4.2.1. Changing Block Size 3.4.2.2. Changing Direction 3.4.2.3. I/O Order 3.4.2.4. Enabling the Variable Streaming FFT 3.4.2.5. Dynamically Changing the FFT Size 3.4.2.6. I/O Order
3.4.3. Buffered Burst x
3.4.3.1. Enabling the Buffered Burst FFT
3.6. FFT IP Core Interfaces and Signals x
3.6.1. Avalon-ST Interfaces in DSP IP Cores 3.6.2. FFT IP Core Avalon-ST Signals
3.6.2. FFT IP Core Avalon-ST Signals x
3.6.2.1. Component Specific Signals
4. Block Floating Point Scaling x
4.1. Possible Exponent Values 4.2. Implementing Scaling 4.3. Unity Gain in an IFFT+FFT Pair
4.2. Implementing Scaling x
4.2.1. Example of Scaling
1. About This IP Core
2. FFT IP Core Getting Started
3. FFT IP Core Functional Description
4. Block Floating Point Scaling
5. Document Revision History
A. FFT IP Core User Guide Document Archive

3.4.1. Streaming FFT

The streaming FFT allows continuous processing of input data, and outputs a continuous complex data stream without the need to halt the data flow in or out of the FFT IP core.

The streaming FFT generates a design with a quad output FFT engine and the minimum number of parallel FFT engines for the required throughput.

A single FFT engine provides enough performance for up to a 1,024-point streaming I/O data flow FFT.


Section Content
Using the Streaming FFT
Changing the Direction on a Block-by-Block Basis
Enabling the Streaming FFT

Level Two Title