F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 1/29/2024
Public

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3.3.1.5. Steps to Run Simulation : Riviera-PRO*

Simulation Flow starting with Intel® Quartus® Prime 22.4 version

  1. Generate the example design
  2. Run the simulation commands below
    1. cd <my_design>/pcie_ed_tb/pcie_ed_tb/sim/aldec
    2. Invoke vsim by using command:
      vsim -c -do rivierapro_setup.tcl
    3. Note: The command below applies only for FASTSIM mode
      set USER_DEFINED_COMPILE_OPTIONS “+define+IP7581SERDES_UX_SIMSPEED”
    4. set USER_DEFINED_ELAB_OPTIONS "-nocvg -dbg -05"
    5. ld
    6. run -all
    7. A successful simulation ends with the following message:
      "Simulation stopped due to successful completion!"