F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 1/29/2024
Public

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Document Table of Contents

2.1.1.2. PIO Application (APPS)

The PIO Application (APPS) component performs the necessary translation between the PCI Express TLPs and simple Avalon-MM writes and reads to the onchip memory. The PIO component interfaces between the Avalon-ST and Avalon- MM. It decodes the TLP headers/data and converts it into Avalon-MM compatible instructions. For a write operation, a single write data TLP is converted into a single AVMM write instruction. While for the read operation, it could be multiple data read back depending on the max payload size boundary. It reads and writes in 512 bits and support contiguous byte enables. These operations are done in the Bursting Avalon Master module in the PIO Application which consists of 4 sub-modules, namely the Scheduler, Read Write Module, Avalon-MM Interface and Completion Module.