SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

Download PDF
ID 683368
Date 10/08/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: ycl1472192322928

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide

2.2. Serial Loopback Design Examples

The serial loopback design examples demonstrate simplex and duplex channel modes.
Figure 12. Serial Loopback with Simplex Mode Block Diagram
Figure 13. Serial Loopback with Simplex Mode Clocking Scheme
Figure 14. Serial Loopback with Duplex Mode Block Diagram
Figure 15. Serial Loopback with Duplex Mode Clocking Scheme
Level Two Title