E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683357
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

3.5.1. Board Connectivity

If you are performing hardware testing on the selected Intel development kits, generate the design example with the appropriate target development kit selected.

Refer to the instructions in Generating the Design.

Note: Running the hardware test with the design generated as-is is only possible when the JESD204C Intel® FPGA IP is configured in duplex data path mode (i.e. with both TX and RX data paths present). Make your own modifications to the design to run the hardware test if generating a simplex data path design.
Table 21.   Intel® Stratix® 10 TX Signal Integrity Development Kit Board ConnectivityThe generated design has pre-assigned pins that target the relevant boards. The table describes the board connectivity of key design ports for all supported target development kits.
Port Name Port Description Board Component Component Description
global_rst_n Global reset

S8

S8 push-button
refclk_core Core PLL reference clock input

U3

Si5341 clock generator (OUT3)
refclk_xcvr Transceiver reference clock input Engineering sample version board revision A and Production version board revision B

U3

Si5341 clock generator (OUT8)
Production version board revision B

U1
Si53311 clock generator (CLK1)
Note: Connect the output of U3 (OUT0) to the input of U1 (J1 and J2) and set SW6 bit 1 to ON to achieved synchronous clock source between reflck_xcvr and reflck_core.
mgmt_clk Control clock

U3

Si5341 clock generator (OUT2) (100 MHz)
tx_serial_data TX serial data Engineering sample version board revision A, up to 8 channels)

U32-1

Intel® Stratix® 10 E-tile banks - 8B (QSFP-DD 1x2)

Engineering sample version board revision A, 9–16 channels)

U32-1 and U75-1

Intel® Stratix® 10 E-tile banks - 8B (QSFP-DD 1x2)

Production version board revision B (up to 16 channels)

J27D

 Intel® Stratix® 10 E-tile banks – 8B (FMC+ connector)
rx_serial_data RX serial data Engineering sample version board revision A, up to 8 channels)

U32-1

Intel® Stratix® 10 E-tile banks - 8B (QSFP-DD 1x2)

Engineering sample version board revision A, 9–16 channels)

U32-1 and U75-1

 Intel® Stratix® 10 E-tile banks - 8B (QSFP-DD 1x2)
Production version board revision B (up to 16 channels)

J27D

 Intel® Stratix® 10 E-tile banks – 8B (FMC+ connector)
user_led[0] GPIO- SPI programming done

U39G

Banks 2 L/M/N ( G31)
user_dip[0] GPIO- internal serial loopback enable

U39G

Banks 2 L/M/N ( G23)
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