3.3. JESD204C Design Example Signals
Signal | Direction | Description |
---|---|---|
Clocks and Resets | ||
mgmt_clk | Input | 100 MHz clock for system management. |
refclk_xcvr | Input | PLL/CDR reference clock for transceiver PHY. |
refclk_core | Input | Core PLL reference clock. Applies the same clock frequency as refclk_xcvr. |
global_rst_n | Input | Global reset signal from the push button. This reset is an active low signal and the deassertion of this signal is synchronous to the rising-edge of mgmt_clk. |
in_sysref | Input | SYSREF signal from external SYSREF generator for JESD204C Subclass 1 implementation. |
sysref_out | Output | SYSREF signal for JESD204C Subclass 1 implementation generated by the FPGA device for design example link initialization purpose only. |
Signal | Direction | Description |
SPI | ||
spi_SS_n[2:0] | Output | Active low, SPI slave select signal. |
spi_SCLK | Output | SPI serial clock. |
spi_sdio
Note: When Generate 3-Wire SPI Module option is enabled.
|
Input/Output | Output data from the master to external slave. Input data from external slave to master. |
spi_MISO
Note: When Generate 3-Wire SPI Module option is not enabled.
|
Input | Input data from external slave to the SPI master. |
spi_MOSI
Note: When Generate 3-Wire SPI Module option is not enabled.
|
Output | Output data from SPI master to the external slave. |
Signal | Direction | Description |
ADC/DAC | ||
tx_serial_data[LINK*L-1:0] | Output | Differential high speed serial output data to DAC. The clock is embedded in the serial data stream. |
tx_serial_data_n[LINK*L-1:0] | ||
rx_serial_data[LINK*L-1:0] | Input | Differential high speed serial input data from ADC. The clock is recovered from the serial data stream. |
rx_serial_data_n[LINK*L-1:0] | ||
Signal | Direction | Description |
General Purpose I/O | ||
user_led[3:0] | Output | Indicates the status for the following conditions:
|
user_dip[3:0] | Input | User mode DIP switch input:
|
Signal |
Direction |
Description |
Out-of-band (OOB) and Status | ||
rx_patchk_data_error[LINK-1:0] | Output |
When this signal is asserted, it indicates pattern checker has detected error. |
rx_link_error[LINK-1:0] | Output |
When this signal is asserted, it indicates JESD204C RX IP has asserted interrupt. |
tx_link_error[LINK-1:0] | Output |
When this signal is asserted, it indicates JESD204C TX IP has asserted interrupt. |
emb_lock_out | Output |
When this signal is asserted, it indicates JESD204C RX IP has achieved EMB lock. |
sh_lock_out | Output |
When this signal is asserted, it indicates JESD204C RX IP sync header is locked. |
Signal |
Direction |
Description |
Avalon Streaming | ||
rx_avst_valid[LINK-1:0] | Input |
Indicates whether the converter sample data to the application layer is valid or invalid.
|
rx_avst_data[LINK-1:0][(TOTAL_SAMPLE*N)-1:0] | Input |
Converter sample data to the application layer. |