E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

Download PDF
ID 683357
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

2.3. Generating the Design

To generate the design example from the IP parameter editor:

  1. Create a project targeting Intel® Stratix® 10 E-tile device family and select the desired device.
  2. In the IP Catalog, Tools > IP Catalog, select JESD204C Intel® FPGA IP .
  3. Specify a top-level name and the folder for your custom IP variation. Click OK.
  4. Select a design from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design.
    Note: If you select another design, the settings of the IP parameters change accordingly. Alternatively, you can also specify your own settings and generate the design.
  5. Under the Example Design tab, specify the design example parameters as described in Design Example Parameters.
  6. Click Generate Example Design.
The software generates all design files in the sub-directories. These files are required to run simulation, compilation, and hardware testing.

Section Content
Design Example Parameters
Directory Structure

Level Two Title