50G Ethernet Design Example User Guide

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ID 683350
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. 50GbE Quick Start Guide 2. Design Example Description 3. Document Revision History
1. 50GbE Quick Start Guide x
1.1. Design Example Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the 50GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the 50GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. 50GbE Design Example Registers
1. 50GbE Quick Start Guide
2. Design Example Description
3. Document Revision History

1.5. Simulating the 50GbE Design Example Testbench

Figure 7. Procedure

Follow these steps to simulate the testbench:

  1. Change to the testbench simulation directory <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table "Steps to Simulate the Testbench".
  3. Analyze the results. The successful testbench sends ten packets, receives ten packets, and displays "Testbench complete."
    Table 3.  Steps to Simulate the Testbench
    Simulator Instructions
    ModelSim In the command line, type vsim -do run_vsim.do

    If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim.do

    Note: The ModelSim* - Intel® FPGA Edition simulator does not have the capacity to simulate this IP core. You must use another supported ModelSim simulator such as ModelSim SE.
    NCSim In the command line, type sh run_ncsim.sh
    VCS In the command line, type sh run_vcs.sh
    Xcelium In the command line, type sh run_xcelium.sh

The successful test run displays output confirming the following behavior:

  1. Waiting for RX clock to settle
  2. Printing PHY status
  3. Sending 10 packets
  4. Receiving 10 packets
  5. Displaying "Testbench complete."

The following sample output illustrates a successful simulation test run: 

#Ref clock is run at 625 MHz so whole numbers can used for all clock periods.
#Multiply reported frequencies by 33/32 to get actual clock frequencies.
#Waiting for RX alignment
#RX deskew locked
#RX lane alignment locked
#TX enabled
#**Sending Packet    1...
#**Sending Packet    2...
#**Sending Packet    3...
#**Sending Packet    4...
#**Sending Packet    5...
#**Sending Packet    6...
#**Sending Packet    7...
#**Received Packet   1...
#**Sending Packet    8...
#**Received Packet   2...
#**Sending Packet    9...
#**Received Packet   3...
#**Sending Packet    10...
#**Received Packet   4...
#**Received Packet   5...
#**Received Packet   6...
#**Received Packet   7...
#**Received Packet   8...
#**Received Packet   9...
#**Received Packet   10... 
#**
#** Testbench complete.
#**
#*****************************************
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