Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

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Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® HLS Compiler Pro Edition Reference Manual 2. Compiler 3. C Language and Library Support 4. Component Interfaces 5. Component Memories (Memory Attributes) 6. Loops in Components 7. Component Concurrency 8. Arbitrary Precision Math Support 9. Component Target Frequency 10. Systems of Tasks 11. Libraries 12. Advanced Hardware Synthesis Controls 13. Intel® High Level Synthesis Compiler Pro Edition Reference Summary A. Advanced Math Source Code Libraries B. Supported Math Functions C. Cyclone® V Restrictions D. Intel® HLS Compiler Pro Edition Reference Manual Archives E. Document Revision History of the Intel® HLS Compiler Pro Edition Reference Manual
1. Intel® HLS Compiler Pro Edition Reference Manual x
1.1. Pending Deprecation of the Intel® HLS Compiler
2. Compiler x
2.1. Intel® HLS Compiler Pro Edition Command Options 2.2. Using Libraries in Your Component 2.3. Compiler Interoperability 2.4. Intel® HLS Compiler Hardware Model
2.3. Compiler Interoperability x
2.3.1. Compiling Your Testbench and Component Separately
3. C Language and Library Support x
3.1. Supported C and C++ Subset for Component Synthesis 3.2. C and C++ Libraries 3.3. Templated and Overloaded Functions 3.4. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
3.3. Templated and Overloaded Functions x
3.3.1. Templated Functions 3.3.2. Overloaded Functions 3.3.3. Function Name Mapping
4. Component Interfaces x
4.1. Component Invocation Interface 4.2. Avalon® Streaming Interfaces 4.3. Pipes 4.4. Avalon® Memory-Mapped Host Interfaces 4.5. Agent Interfaces 4.6. Stable Component Parameters 4.7. Global Variables 4.8. Structs in Component Interfaces 4.9. Reset Behavior
4.1. Component Invocation Interface x
4.1.1. Scalar Parameters 4.1.2. Pointer and Reference Parameters 4.1.3. Interface Definition Example: Component Invocation Interface Control Attributes 4.1.4. Interface Definition Example: Component with Both Scalar and Pointer Arguments
4.3. Pipes x
4.3.1. The pipe Class and Its Use
4.4. Avalon® Memory-Mapped Host Interfaces x
4.4.1. Memory-Mapped Host Testbench Constructor 4.4.2. Implicit and Explicit Examples of Describing a Memory Interface 4.4.3. Avalon® Memory-Mapped Host Interfaces and Load-Store Units
4.4.3. Avalon® Memory-Mapped Host Interfaces and Load-Store Units x
4.4.3.1. Load-Store Unit Types 4.4.3.2. Memory-Access Coalescing and Load-Store Units
4.5. Agent Interfaces x
4.5.1. Control and Status Register (CSR) Agent 4.5.2. Agent Memories
5. Component Memories (Memory Attributes) x
5.1. Static Variables
6. Loops in Components x
6.1. Loop Initiation Interval (ii Pragma) 6.2. Loop-Carried Dependencies (ivdep Pragma) 6.3. Loop Coalescing (loop_coalesce Pragma) 6.4. Loop Unrolling (unroll Pragma) 6.5. Loop Concurrency (max_concurrency Pragma) 6.6. Loop Iteration Speculation (speculated_iterations Pragma) 6.7. Loop Pipelining Control (disable_loop_pipelining Pragma) 6.8. Loop Interleaving Control (max_interleaving Pragma) 6.9. Loop Fusion
6.9. Loop Fusion x
6.9.1. Loop Fusion Control (loop_fuse Pragma) 6.9.2. Loop Fusion Exemption (nofusion pragma)
7. Component Concurrency x
7.1. Serial Equivalence within a Memory Space or I/O 7.2. Concurrency Control (hls_max_concurrency Attribute) 7.3. Component Pipelining Control (hls_disable_component_pipelining Attribute)
8. Arbitrary Precision Math Support x
8.1. Declaring ac_int Data Types 8.2. Declaring ac_fixed Data Types 8.3. Declaring ac_complex Data Types 8.4. AC Data Types and Native Compilers 8.5. Declaring hls_float Data Types
8.1. Declaring ac_int Data Types x
8.1.1. Important Usage Information on the ac_int Data Type 8.1.2. Integer Promotion and ac_int Data Types 8.1.3. Debugging Your Use of the ac_int Data Type
8.2. Declaring ac_fixed Data Types x
8.2.1. Arbitrary Precision Fixed-Point Literals in Operations
8.5. Declaring hls_float Data Types x
8.5.1. Operators and Return Types Supported by the hls_float Data Type 8.5.2. Additional Data Types Provided By hls_float.h
9. Component Target Frequency x
9.1. Effects of Specifying Target II and Target fMAX
10. Systems of Tasks x
10.1. Task Functions 10.2. Internal Streams 10.3. System of Tasks Simulation
11. Libraries x
11.1. Static-Object Libraries 11.2. Creating a Static-Object Library 11.3. Creating Objects From HLS Code 11.4. Creating Objects From RTL Code 11.5. Packaging Object Files Into a Library
11.3. Creating Objects From HLS Code x
11.3.1. Creating an Object File From HLS Code 11.3.2. Supported OpenCL* Language Constructs
11.4. Creating Objects From RTL Code x
11.4.1. RTL Modules and the HLS Pipeline 11.4.2. Creating a Static-Object File from an RTL Module
11.4.1. RTL Modules and the HLS Pipeline x
11.4.1.1. Integration of an RTL Module into the HLS Pipeline 11.4.1.2. RTL Module Interfaces 11.4.1.3. RTL Reset and Clock Signals 11.4.1.4. Object Manifest File Syntax 11.4.1.5. Mapping HLS Data Types to RTL Signals 11.4.1.6. HLS Emulation Models for RTL-Based Functions 11.4.1.7. Potential Incompatibility between RTL Modules and Partial Reconfiguration 11.4.1.8. Stall-Free RTL 11.4.1.9. RTL Module Restrictions and Limitations for HLS Libraries
11.4.1.2. RTL Module Interfaces x
11.4.1.2.1. RTL Module Interface Signals
11.4.1.3. RTL Reset and Clock Signals x
11.4.1.3.1. Intel Agilex® 7 and Intel® Stratix® 10 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Modules
11.4.1.4. Object Manifest File Syntax x
11.4.1.4.1. XML Elements for ATTRIBUTES 11.4.1.4.2. XML Elements for INTERFACE 11.4.1.4.3. XML Elements for RESOURCES
11.4.1.4.1. XML Elements for ATTRIBUTES x
11.4.1.4.1.1. Interaction Between ALLOW_MERGINGand HAS_SIDE_EFFECTS Elements
12. Advanced Hardware Synthesis Controls x
12.1. Hardware Implementation Control for Math Functions 12.2. The hls_fpga_reg() Function
12.1. Hardware Implementation Control for Math Functions x
12.1.1. Math Function Hardware Implementation Summary 12.1.2. The --dsp-mode Command Option 12.1.3. The ihc::math_dsp_control Function
13. Intel® High Level Synthesis Compiler Pro Edition Reference Summary x
13.1. Intel® HLS Compiler Pro Edition i++ Command-Line Arguments 13.2. Intel® HLS Compiler Pro Edition Header Files 13.3. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros 13.4. Intel® HLS Compiler Pro Edition Keywords 13.5. Intel® HLS Compiler Pro Edition Simulation API (Testbench Only) 13.6. Intel® HLS Compiler Pro Edition Component Memory Attributes 13.7. Intel® HLS Compiler Pro Edition Loop Pragmas 13.8. Intel® HLS Compiler Pro Edition Scope Pragmas 13.9. Intel® HLS Compiler Pro Edition Component Attributes 13.10. Intel® HLS Compiler Pro Edition Component Default Interfaces 13.11. Intel® HLS Compiler Pro Edition Component Invocation Interface Control Attributes 13.12. Intel® HLS Compiler Pro Edition Component Macros 13.13. Intel® HLS Compiler Pro Edition Systems of Tasks API 13.14. Intel® HLS Compiler Pro Edition Pipes API 13.15. Intel® HLS Compiler Pro Edition Streaming Input Interfaces 13.16. Intel® HLS Compiler Pro Edition Streaming Output Interfaces 13.17. Intel® HLS Compiler Pro Edition Memory-Mapped Interfaces 13.18. Intel® HLS Compiler Pro Edition Load-Store Unit Control 13.19. Intel® HLS Compiler Pro Edition Arbitrary Precision Data Types
13.13. Intel® HLS Compiler Pro Edition Systems of Tasks API x
13.13.1. ihc::stream Class
A. Advanced Math Source Code Libraries x
A.1. Random Number Generator Library A.2. Matrix Multiplication Library A.3. Cholesky Decomposition Library
B. Supported Math Functions x
B.1. Math Functions Provided by the math.h Header File B.2. Math Functions Provided by the extendedmath.h Header File B.3. Math Functions Provided by the ac_fixed_math.h Header File B.4. Math Functions Provided by the hls_float.h Header File B.5. Math Functions Provided by the hls_float_math.h Header File B.6. Default Rounding Schemes and Subnormal Number Support
1. Intel® HLS Compiler Pro Edition Reference Manual
2. Compiler
3. C Language and Library Support
4. Component Interfaces
5. Component Memories (Memory Attributes)
6. Loops in Components
7. Component Concurrency
8. Arbitrary Precision Math Support
9. Component Target Frequency
10. Systems of Tasks
11. Libraries
12. Advanced Hardware Synthesis Controls
13. Intel® High Level Synthesis Compiler Pro Edition Reference Summary
A. Advanced Math Source Code Libraries
B. Supported Math Functions
C. Cyclone® V Restrictions
D. Intel® HLS Compiler Pro Edition Reference Manual Archives
E. Document Revision History of the Intel® HLS Compiler Pro Edition Reference Manual

E. Document Revision History of the Intel® HLS Compiler Pro Edition Reference Manual

Document Version Intel® HLS Compiler Pro Edition Version Changes
2023.10.02 23.3
  • Maintenance release.

    Updated <quartus_installdir> path information for Version 23.3.

2023.06.26 23.2
  • Maintenance release.

    Updated <quartus_installdir> path information for Version 23.2.

2023.06.02 23.1
2023.05.26 23.1
2023.05.05 23.1
2023.04.03 23.1

  • Updated <quartus_installdir> path information for Version 23.1.

  • Updated product family name to "Intel Agilex 7."
2022.12.19 22.4
  • Added pending deprecation notice.
  • Updated <quartus_installdir> path information for Version 22.4.
2022.09.23 22.3
  • Maintenance release.

    Updated <quartus_installdir> path information for Version 22.3.

2022.06.20 22.2
2022.03.28 22.1
  • Enhanced the description of the ihc::firstSymbolInHighOrderBits parameter to indicate that effect of setting of this parameter can be seen only in the simulation waveforms of your design.
  • Updated Memory-Mapped Host Testbench Constructor to remove description of the use_socket parameter. This parameter is not required.
2021.12.13 21.4
2021.10.04 21.3
  • Updated the description of the --simulator command option to include Siemens* EDA Questa* support.
2021.05.21 21.2
  • Added limitation for casting hls_float datatypes to unsigned integer datatypes to Arbitrary Precision Math Support.
  • Revised references to Avalon Interfaces to align with new Avalon Interconnect terminology. Avalon master interfaces are now Avalon host interfaces, and Avalon slave interfaces are now Avalon agent interfaces.
  • Renamed the interfaces to align with the new Avalon Interconnect terminology. Interfaces using the old terminology are deprecated. Interfaces using the new terminology have been introduced as replacements as follows:
    Table 82.   Intel® HLS Compiler Interface Changes
    Deprecated Interface Replacement Interface
    hls_avalon_slave_component hls_avalon_agent_component
    hls_avalon_slave_register_argument hls_avalon_agent_register_argument
    hls_avalon_slave_memory_argument hls_avalon_agent_memory_argument
    mm_master mm_host

    If you use the deprecated interfaces, you might get warning messages when you compile your component.

2021.03.29 21.1
2020.12.14 20.4
2020.09.28 20.3
2020.06.22 20.2
2020.05.13 20.1
2020.04.13 20.1
2020.02.10 19.4
2020.01.27 19.4
2019.12.16 19.4

Document Revision History for Intel® HLS Compiler Reference Manual

Previous versions of the Intel® HLS Compiler Reference Manual contained information for both Intel® HLS Compiler Standard Edition and Intel® HLS Compiler Pro Edition.

Document Version Intel® Quartus® Prime Version Changes
2019.09.30 19.3
2019.09.10 19.2
2019.07.01 19.2
2019.06.04 19.1
  • In Slave Memories, clarified the use of memory attributes for slave memories.
  • In Component Memories (Memory Attributes), clarified memory attributes support in Intel® HLS Compiler Pro Edition and Intel® HLS Compiler Standard Edition.
2019.05.03 19.1
2019.04.01 19.1
2019.01.03 18.1.1
2018.12.24 18.1.1
  • Removed information about the "HLS/iostream" header file. The function provided by this header file is replaced by using the standard C++ iostream header and the HLS_SYNTHESIS macro.
  • Added description of the HLS_SYNTHESIS macro to C and C++ Libraries.
2018.12.24 18.1
2018.09.24 18.1
  • The Intel® HLS Compiler has a new front end. For a summary of the changes introduced by this new front end, see Improved Intel HLS Compiler Front End in the Intel® HLS Compiler Version 18.1 Release Notes.
  • The --promote-integers flag and the best_practices/integer_promotion tutorial are no longer supported in Pro Edition because integer promotion is now done by default. The flag and tutorial are still supported in Standard Edition.
  • Components invoked with the hls_avalon_slave_component argument must take slave or stable arguments. If the component arguments are not slave or stable arguments, compiling the component generates an error message. The description of the hls_avalon_slave_component argument in Component Invocation Interface Control Attributes and Quick Reference now reflects that requirement.
  • In Loops in Components, clarified the pragma statements that apply to loops must immediately precede the loop that the pragma applies to.
  • In Declaring ac_int Data Types, added initialization requirement for ac_int variables larger than 64 bits. You must use ac::init_array constructors to initialize ac_int variables larger than 64 bits.
  • In Static Variables, removed the restriction on applying memory attributes to file-scoped static variables. Both file-scoped and function-scoped static variables can have memory attributes applied to them.
2018.07.08 18.0
  • In Static Variables, highlighted paragraph that says that memory attributes applied to static variables work only if the static variable is declared within the component function.
  • In Control and Status Register (CSR) Agent, corrected a typo. The sentence " You do not need to use the hls_avalon_slave_component attribute to use the hls_avalon_slave_component attribute" was corrected to say "You do not need to use the hls_avalon_slave_component attribute to use the hls_avalon_slave_register_argument attribute".
2018.05.07 18.0
  • Starting with Intel® Quartus® Prime Version 18.0, the features and devices supported by the Intel® HLS Compiler depend on what edition of Intel® Quartus® Prime you have. Intel® HLS Compiler publications now use icons to indicate content and features that apply only to a specific edition as follows:
    Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Pro Edition.
    Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Standard Edition.
  • Corrected the code example in Intel® HLS Compiler Streaming Input Interfaces Code Example. The corrected line is int x = a.tryRead(success); (was int x = a.tryRead(&success);).
  • Added a footnote to the [FB519042-march MAX10[FB519042] option in Command Options] about a prerequisite required before you synthesize your component IP for Intel® MAX® 10 devices.
2017.12.22 17.1.1
  • Updated hls_avalon_slave_memory_argument(N) description in Slave Memories to include the description that the parameter value N is the size of the memory in bytes.
2017.11.06 17.1
  • Updated Supported Math Functions as follows:
    • Noted that the HLS/extendedmath.h header file is supported only by the Intel® HLS Compiler, not by the GCC or MSVC compilers.
    • Added popcount to the list functions supported by the HLS/extendedmath.h header file.
    • Expanded list of functions provided by HLS/extendedmath.h to explicitly list double-precision and single-precision floating point versions of the functions.
    • Added a list of popcount function variations available for different data types.
  • Reorganized the overall structure of the book, breaking up chapter 1 into smaller chapters and changing the order of the chapters.
  • Updated mentions of the HLS or i++ installation directory to use the Intel® Quartus® Prime Design Suite installation directory as the starting point.
  • Moved the following content to Intel® High Level Synthesis Compiler Best Practices Guide:
2017.06.23 —
  • Updated Static Variables to add information about static variable initialization and how to control it.
  • Minor changes and corrections.
2017.06.09 —
  • Removed all mentions of --device compiler option. This option has been replaced by the changed function of the -march compiler option. See Intel HLS Compiler Pro Edition Command Options for details about the changed function of the -march compiler option.
2017.02.03 —
  • In Scalar Parameters and Avalon Streaming Interfaces, updated information in the Available Scalar Parameters for Avalon-ST Interfaces table.
  • In Pointer Parameters, Reference Parameters, and Avalon Memory-Mapped Master Interfaces, updated information in the Available Template Arguments for Configuration of the Avalon-MM Interface table.
  • Added new information to Global Variables about area usage and optimizing for global constants, pointers, and variables.
2016.11.30 —
  • In HLS Compiler Command Options, modified the table Command Options that Customize Compilation in the following manner:
    • Removed the --rtl-only command option and its description because it is no longer in use.
    • Added the --simulator <name> command option and its description.
    • Remove the -g command option because the HLS compiler now generates debug information in reports by default for both Windows and Linux. In addition, debug data is available by default in final binaries for Linux.
  • In Pointer Parameters, Reference Parameters, and Avalon Memory-Mapped Master Interfaces, added information on the altera::align<value> template argument in the table.
  • Added the topics Memory-Mapped Test Bench Constructor and Implicit and Explicit Examples of Creating a Memory-Mapped Master Test Bench.
  • In Usage Examples of Component Invocation Protocol Macros, replaced component invocation protocol attributes in the code examples with their corresponding macros.
  • Added the line #include "HLS/hls.h" to the code snippets in the following sections:
    • Usage Examples of Interface Synthesis Macros
    • Usage Examples of Component Invocation Protocol Macros
  • Added the topic Arbitrary Precision Integer Support to introduce the ac_int datatype and the Intel-provided ac_int.h header file. Included the following subtopics:
    • Defining the ac_int Datatype in Your Component for Arbitrary Precision Integer Support
    • Important Usage Information on the ac_int Datatype
  • Updated the content in Area Minimization and Control of On-Chip Memory Architecture:
    • Replaced the numreadports(n) and numwriteports(n) entries the Attributes for Controlling On-Chip Memory Architecture table with a single numports_readonly_writeonly(m,n) entry.
    • Added information on the hls_simple_dual_port_memory macro.
    • Added information on the hls_merge ("label","direction") and the hls_bankbits(b0, b1, ..., bn) attributes.
  • Added example use cases for the hls_merge("label","direction") and the hls_bankbits(b0, b1, ..., bn) attributes.
  • Added the topic Relationship between hls_bankbits Specifications and Memory Address Bits to explain the derivation of a memory address in the presence of the hls_bankbits and hls_bankwidth attributes.
2016.09.12 — Initial release.
Level Two Title