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1. About This IP Core
2. Getting Started With the 100G Interlaken IP Core
3. 100G Interlaken IP Core Parameter Settings
4. Functional Description
5. 100G Interlaken IP core Signals
6. 100G Interlaken IP Core Register Map
7. 100G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 100G Interlaken IP core
10. 100G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 100G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 100G Ethernet Traffic
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Specifying the 100G Interlaken IP Core Parameters and Options
2.3. Files Generated for Arria V GZ and Stratix V Variations
2.4. Files Generated for Intel® Arria® 10 Variations
2.5. Simulating the 100G Interlaken IP Core
2.6. Integrating Your IP Core in Your Design
2.7. Compiling the Full Design and Programming the FPGA
2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
3.1. Number of Lanes
3.2. Meta Frame Length in Words
3.3. Data Rate
3.4. Transceiver Reference Clock Frequency
3.5. Include Advanced Error Reporting and Handling
3.6. Enable M20K ECC Support
3.7. Include Diagnostic Features
3.8. Enable Native PHY Debug Master Endpoint (NPDME)
3.9. Include In-Band Flow Control Block
3.10. Number of Calendar Pages
3.11. TX Scrambler Seed
3.12. Transfer Mode Selection
3.13. Data Format
5.1. 100G Interlaken IP Core Clock Interface Signals
5.2. 100G Interlaken IP Core Reset Interface Signals
5.3. 100G Interlaken IP Core User Data Transfer Interface Signals
5.4. 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
5.5. 100G Interlaken IP Core Management Interface
5.6. Device Dependent Signals
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2.2. Specifying the 100G Interlaken IP Core Parameters and Options
The 100G Interlaken parameter editor allows you to quickly configure your custom IP variation. You specify IP core options and parameters in the Quartus® Prime software.
The 100G Interlaken IP core is not supported in Platform Designer (Standard). You must use the IP Catalog accessible from the Quartus® Prime Tools menu.
The 100G Interlaken IP core does not support VHDL simulation models. Intel® recommends that you specify the Verilog HDL for both synthesis and simulation models.
- In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.
- Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .qsys. Click OK.
Note: For Arria V GZ and Stratix V variations, you are prompted to specify an IP variation file type. To generate the demonstration testbench and example design, you must select the Verilog HDL and specify the Verilog file extension (.v).
- Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to 100G Interlaken IP Core Parameter Settings for information about specific IP core parameters.
- Specify parameters defining the IP core functionality, port configurations, and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
- For Intel® Arria® 10 variations, follow these steps:
- Click Generate HDL. The Generation dialog box appears.
- Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
Note: To generate the demonstration testbench and example design, you must specify Verilog HDL for both synthesis and simulation models.
- Optionally, click the Generate Example Design button in the parameter editor to generate a testbench and a hardware example design that targets the Intel® Arria® 10 Transceiver Signal Integrity Development Kit.
- Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.
- For Arria V GZ and Stratix V variations, follow these steps:
- Click Finish. The Generation dialog box appears.
- If you want to generate a demonstration testbench and example design for your IP core variation, turn on Generate example design.
- Click Generate.
- Click Exit. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.
- After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.