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1. About This IP Core
2. Getting Started With the 100G Interlaken IP Core
3. 100G Interlaken IP Core Parameter Settings
4. Functional Description
5. 100G Interlaken IP core Signals
6. 100G Interlaken IP Core Register Map
7. 100G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 100G Interlaken IP core
10. 100G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 100G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 100G Ethernet Traffic
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Specifying the 100G Interlaken IP Core Parameters and Options
2.3. Files Generated for Arria V GZ and Stratix V Variations
2.4. Files Generated for Intel® Arria® 10 Variations
2.5. Simulating the 100G Interlaken IP Core
2.6. Integrating Your IP Core in Your Design
2.7. Compiling the Full Design and Programming the FPGA
2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
3.1. Number of Lanes
3.2. Meta Frame Length in Words
3.3. Data Rate
3.4. Transceiver Reference Clock Frequency
3.5. Include Advanced Error Reporting and Handling
3.6. Enable M20K ECC Support
3.7. Include Diagnostic Features
3.8. Enable Native PHY Debug Master Endpoint (NPDME)
3.9. Include In-Band Flow Control Block
3.10. Number of Calendar Pages
3.11. TX Scrambler Seed
3.12. Transfer Mode Selection
3.13. Data Format
5.1. 100G Interlaken IP Core Clock Interface Signals
5.2. 100G Interlaken IP Core Reset Interface Signals
5.3. 100G Interlaken IP Core User Data Transfer Interface Signals
5.4. 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
5.5. 100G Interlaken IP Core Management Interface
5.6. Device Dependent Signals
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4.1.4. Management Interface
The management interface provides access to the 100G Interlaken IP core internal status and control registers. This interface does not provide access to the hard PCS registers on the device.
The management interface complies with the Avalon Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications.
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