100G Interlaken Intel® FPGA IP User Guide

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ID 683338
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. Getting Started With the 100G Interlaken IP Core 3. 100G Interlaken IP Core Parameter Settings 4. Functional Description 5. 100G Interlaken IP core Signals 6. 100G Interlaken IP Core Register Map 7. 100G Interlaken IP Core Test Features 8. Advanced Parameter Settings 9. Out-of-Band Flow Control in the 100G Interlaken IP core 10. 100G Interlaken Intel® FPGA IP User Guide Archives 11. Document Revision History for 100G Interlaken Intel® FPGA IP User Guide A. Performance and Fmax Requirements for 100G Ethernet Traffic
1. About This IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grade Support 1.6. Release Information
1.1. Features x
1.1.1. IP Core Supported Combinations of Number of Lanes and Data Rate 1.1.2. IP Core Theoretical Raw Aggregate Bandwidth
2. Getting Started With the 100G Interlaken IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 100G Interlaken IP Core Parameters and Options 2.3. Files Generated for Arria V GZ and Stratix V Variations 2.4. Files Generated for Intel® Arria® 10 Variations 2.5. Simulating the 100G Interlaken IP Core 2.6. Integrating Your IP Core in Your Design 2.7. Compiling the Full Design and Programming the FPGA 2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. Transceiver Logical Channel Numbering 2.6.3. Adding the Reconfiguration Controller 2.6.4. Adding the External PLL
2.6.3. Adding the Reconfiguration Controller x
2.6.3.1. Generating the Reconfiguration Controller 2.6.3.2. Connecting the Reconfiguration Controller to the IP Core
3. 100G Interlaken IP Core Parameter Settings x
3.1. Number of Lanes 3.2. Meta Frame Length in Words 3.3. Data Rate 3.4. Transceiver Reference Clock Frequency 3.5. Include Advanced Error Reporting and Handling 3.6. Enable M20K ECC Support 3.7. Include Diagnostic Features 3.8. Enable Native PHY Debug Master Endpoint (NPDME) 3.9. Include In-Band Flow Control Block 3.10. Number of Calendar Pages 3.11. TX Scrambler Seed 3.12. Transfer Mode Selection 3.13. Data Format
4. Functional Description x
4.1. Interfaces Overview 4.2. High Level Block Diagram 4.3. Clocking and Reset Structure for IP Core 4.4. Interleaved and Packet Modes 4.5. Dual Segment Mode 4.6. M20K ECC Support 4.7. 100G Interlaken IP Core Transmit Path 4.8. 100G Interlaken IP Core Receive Path
4.1. Interfaces Overview x
4.1.1. Application Interface 4.1.2. Interlaken Interface 4.1.3. Out‑of‑Band Flow Control Interface 4.1.4. Management Interface 4.1.5. Transceiver Control Interfaces
4.1.5. Transceiver Control Interfaces x
4.1.5.1. Transceiver Reconfiguration Controller Interface 4.1.5.2. Intel® Arria® 10 External PLL Interface 4.1.5.3. Intel® Arria® 10 Transceiver Reconfiguration Interface
4.3. Clocking and Reset Structure for IP Core x
4.3.1. 100G Interlaken IP Core Clock Signals 4.3.2. IP Core Reset 4.3.3. IP Core Reset Sequence with the Reconfiguration Controller
4.7. 100G Interlaken IP Core Transmit Path x
4.7.1. 100G Interlaken IP Core Transmit User Data Interface Examples 4.7.2. 100G Interlaken IP Core In-Band Calendar Bits on Transmit Side 4.7.3. 100G Interlaken IP Core Transmit Path Blocks
4.7.1. 100G Interlaken IP Core Transmit User Data Interface Examples x
4.7.1.1. 100G Interlaken IP Core Interleaved Mode (Segmented Mode) Example 4.7.1.2. 100G Interlaken IP Core Packet Mode Operation Example 4.7.1.3. 100G Interlaken IP Core Back-Pressured Packet Transfer Example 4.7.1.4. 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit Example
4.7.3. 100G Interlaken IP Core Transmit Path Blocks x
4.7.3.1. 100G Interlaken IP Core TX Transmit Buffer 4.7.3.2. 100G Interlaken IP Core TX MAC 4.7.3.3. 100G Interlaken IP Core TX PCS 4.7.3.4. 100G Interlaken IP Core TX PMA
4.8. 100G Interlaken IP Core Receive Path x
4.8.1. 100G Interlaken IP Core Receive User Data Interface Examples 4.8.2. 100G Interlaken IP Core RX Errored Packet Handling 4.8.3. In-Band Calendar Bits on the 100G Interlaken IP Core Receiver User Data Interface 4.8.4. 100G Interlaken IP Core Receive Path Blocks
4.8.1. 100G Interlaken IP Core Receive User Data Interface Examples x
4.8.1.1. 100G Interlaken IP Core Receiver Side Example 4.8.1.2. 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive Example
4.8.2. 100G Interlaken IP Core RX Errored Packet Handling x
4.8.2.1. 100G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits
4.8.4. 100G Interlaken IP Core Receive Path Blocks x
4.8.4.1. 100G Interlaken IP Core RX PMA 4.8.4.2. 100G Interlaken IP Core RX PCS 4.8.4.3. 100G Interlaken IP Core RX MAC 4.8.4.4. 100G Interlaken IP Core RX Regroup Block
5. 100G Interlaken IP core Signals x
5.1. 100G Interlaken IP Core Clock Interface Signals 5.2. 100G Interlaken IP Core Reset Interface Signals 5.3. 100G Interlaken IP Core User Data Transfer Interface Signals 5.4. 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals 5.5. 100G Interlaken IP Core Management Interface 5.6. Device Dependent Signals
5.6. Device Dependent Signals x
5.6.1. Transceiver Reconfiguration Controller Interface Signals 5.6.2. Intel® Arria® 10 External PLL Interface Signals 5.6.3. Intel® Arria® 10 Transceiver Reconfiguration Interface Signals
7. 100G Interlaken IP Core Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode 7.3. PRBS Generation and Validation 7.4. CRC32 Error Injection 7.5. CRC24 Error Injection
7.3. PRBS Generation and Validation x
7.3.1. Setting up PRBS Mode in Arria V and Stratix V Devices 7.3.2. Setting up PRBS Mode in Intel® Arria® 10 Devices
8. Advanced Parameter Settings x
8.1. Hidden Parameters 8.2. Modifying Hidden Parameter Values
8.1. Hidden Parameters x
8.1.1. Include Temp Sense 8.1.2. RXFIFO Address Width 8.1.3. SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping)
9. Out-of-Band Flow Control in the 100G Interlaken IP core x
9.1. Out-of-Band Flow Control Block Clocks 9.2. TX Out‑of‑Band Flow Control Signals 9.3. RX Out-of-Band Flow Control Signals
1. About This IP Core
2. Getting Started With the 100G Interlaken IP Core
3. 100G Interlaken IP Core Parameter Settings
4. Functional Description
5. 100G Interlaken IP core Signals
6. 100G Interlaken IP Core Register Map
7. 100G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 100G Interlaken IP core
10. 100G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 100G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 100G Ethernet Traffic

4.8.1.2. 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive Example

Figure 18. Dual Segment Data Transfer on Receive Interface in Interleaved Mode

This example illustrates the expected behavior of the 100G Interlaken IP core application interface receive signals during dual segment transfers of three data bursts in interleaved mode. The 100G Interlaken IP core can generate dual segment data transfers only if you configure the IP core in dual segment mode.

The figure shows three data bursts in dual segment mode on the RX user data transfer interface. In cycle 1, the IP core asserts irx_sop[1] and irx_sob[1], indicating that this cycle is both the start of the burst and the start of the packet, and that data starts from the most significant byte of the data symbol. The IP core drives the value of 2 on irx_chan to indicate the data targets channel 2.

In cycle 2, the following two events occur:

  • The first data burst completes. The IP core asserts irx_eob, indicating the data the IP core transfers to the application in this clock cycle is the end of the burst. The value the IP core drives on irx_num_valid[7:4] indicates that one word in this data symbol is valid data associated with this burst. In addition, the IP core drives irx_eopbits to the value of 4'b0000 to indicate that the data the IP core transfers to the application in this clock cycle is not the end of the packet.
  • A second data burst starts at Word 3, as is allowed in dual segment mode. The IP core asserts irx_sop[0] and irx_sob[0], indicating that this cycle is both the start of the burst and the start of the packet, and that data in this burst and packet starts from Byte 31 of the data symbol. The IP core drives the value of 3 on irx_chan to indicate the data targets channel 3. The value of irx_num_valid[3:0] is 4'b0100, indicating this data transfer is a dual segment data transfer—that it begins at Word 3. The value of irx_num_valid[7:4] has no relevance for the data words in this burst that appear in this data symbol, except to indicate the previous burst includes no data in these words of the data symbol (Words 3 through 0), and therefore, that they are available for the second data burst. As is required, the dual segment data transfer places valid data in all four words in the least significant half of the data symbol.

In cycles 3 and 4, the second data burst continues with no EOB or EOP indication. The application should not sample the value of irx_chan in these clock cycles. The value on irx_num_valid[7:4] indicates that all eight words in each of these data symbols are valid data associated with this burst.

In cycle 5, the following two events occur:

  • The second data burst completes. The IP core asserts irx_eob, indicating the data transfered in this clock cycle is the end of the burst. The value the IP core drives on irx_num_valid[7:4] indicates that four words in this data symbol are valid data associated with this burst. In addition, the value the IP core drives on irx_eopbits indicates the data is the end of the packet, and that all eight bytes of the final data word are valid data bytes.
  • A third data burst starts at Word 3, as is allowed in dual segment mode. The IP core asserts irx_sob[0], indicating that this cycle is the start of the burst and that data in this burst starts from Byte 31 of the data symbol. However, the IP core does not assert irx_sop[0], indicating this burst is not the first burst in the packet. The value the IP core drives on irx_chan indicates the data targets channel 2. Therefore, we can conclude this data burst is the second burst in a packet that targets channel 2. The value the IP core drives on irx_num_valid[3:0] is 4'b0100, indicating this data transfer is a dual segment data transfer—that it begins at Word 3. The value of irx_num_valid[7:4] has no relevance for the data words in this burst that appear in this data symbol, except to indicate the previous burst includes no data in these words of the data symbol (Words 3 through 0), and therefore, that they are available for the second data burst. As is required, the dual segment data transfer places valid data in all four words in the least significant half of the data symbol.

In cycle 6, the third data burst completes. The IP core asserts irx_eob, indicating the data transfered in this clock cycle is the end of the burst. The value on irx_num_valid[7:4] indicates that five words in this data symbol are valid data associated with this burst. In addition, the value the IP core drives on irx_eopbits indicates the data is the end of the packet, and that all eight bytes of the final data word are valid data bytes. Because the data from this burst occupies words 7 through 3 of the data symbol, another burst cannot start in the current data symbol.

By default, the RX user data transfer interface can generate interleaved data. However, the IP core can also transfer a packet without interleaving—if the IP core does not toggle the channel number during the packet transfer, the packet is not interleaved with another packet. In this case, the IP core still asserts the irx_sob and irx_eob signals correctly to maintain the proper burst boundaries.

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