4.1.2.1.2. Valid, Channel, and Data Examples

DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

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4.1.2.1.2. Valid, Channel, and Data Examples

In your design you have a clock rate N (MHz) and a per-channel sample rate M (Msps). If N = M, DSP Builder receives one new data sample per channel every clock cycle.

Figure 4. Single Channel DesignThe frame length, which is the number of clock cycles between data updates for a particular channel, is 1. The out channel count starts (from zero) every clock cycle. sPQ = the Qth data sample for channel P.

Figure 5. Multichannel DesignIf the data is spread across multiple wires, even for multiple channels, the frame length is 1. The channel signal number, which is a channel synchronization counter, rather than an explicit number expressing the actual channels, is again zero on each clock cycle.

Figure 6. Single Channel n > M DSP Builder receives new data samples only every N/M clocks. If N = 300 MHz and M = 100Msps, DSP Builder gives new data every 3 clock cycles. DSP Builder does not know what the data is on the intervening clocks, and sets the valid to low (0). X is unknown or do not care. The frame length is 3 because of a repeating pattern of channel data every 3 clock cycles

Figure 7. Single Channel n > M and Two Data Channels If N = 300 MHz and M = 100 Msps, with two data channels, the data wire carries the sample for the first channel, the data for the second channel, then a cycle of unknown: The channel signal now increments as DSP Builder receives the different channel data through the frame.

Figure 8. Three Channels If N = 300 MHz and M = 100Msps, the frame is full along the single data wire.

Figure 9. Four ChannelsThe data now spreads across multiple data signals as one wire is not enough to transmit four channels of data in three clock cycles. DSP Builder attempts to distribute the channels evenly on the wires that it has to use:

Figure 10. Five ChannelsThe data spreads across two data signals that transmit five channels of data in three clock cycles. DSP Builder packs the five channels of data as three on the first wire and two on the second. The channel signal still counts up from zero at the start of each frame and that it specifies a channel synchronization count, rather than expressing all the channels received on a particular clock (which requires as many channel signals as data signals). The valid signal also remains one-dimensional, which can under-specify the validity of the concurrent data if, in a particular frame, channel 0 is valid but channel 3 (received on the same clock) is not. In the five-channel example, DSP Builder receives data for channel 2 on the first data signal at the same time as the invalid data on the second data signal. You require some knowledge of the number of channels transmitted.

Figure 11. Single Channel n < M DSP Builder receives multiple (M/N) data samples for a particular channel every clock cycle—super-sample data. If N = 200 MHz and M = 800 Msps, you see a single channel with four new data samples every clock

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DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

4.1.2.1.2. Valid, Channel, and Data Examples