15.2.1. DFT (DFT)

DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

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Date 12/12/2022

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15.2.1. DFT (DFT)

The DFT block performs a discrete Fourier transform (DFT) or an inverse DFT (IDFT) of a fixed-point complex input sequence and produces a fixed-point complex output sequence. The demo_dft.mdl example design demonstrates the DFT block.

You can specify the transform length (DFT size) at runtime (on a block-by-block basis) to any one of the 53 sizes specified by 3GPP TS 36.101 version 8.29.0 Release 8 (Table 1). In addition to the DFT block, the DSP Builder block-set provides an FFT block. However, the FFT block cannot support these 53 sizes as it is limited to powers of two sizes.

The DFT block is a back-to-back streaming DFT. This design allows the block to process DFTs continuously, with no breaks required when the DFT size changes, and no busy periods when it is unable to accept new input.

When the DFT block pipeline is empty, the input-to-output latency for a DFT operation (first input to first output) depends only on the current DFT size and the pipeline overhead. The pipeline overhead is constant for all dynamic DFT sizes.

When the pipeline is not empty, the input-to-output latency for a DFT operation is affected by the current contents of the pipeline. The DFT block implements a queueing system to prevent small DFT operations from overtaking (or colliding with) larger ones. For example, if a 12-point DFT enters the pipeline immediately after a 3,240-point DFT, it can’t produce its first output until the larger DFT has output all 3,240 points.

Table 93. DFT Block Supported Sizes The DFT block supports the following 53 sizes specified by 3GPP TS 36.101 version 8.29.0 Release 8:
12	120	324	648	1,152	1,800	2,880
24	144	360	720	1,200	1,920	2,916
36	180	384	768	1,296	1,944	3,000
48	192	432	864	1,440	2,160	3,072
60	216	480	900	1,500	2,304	3,240
72	240	540	960	1,536	2,400
96	288	576	972	1,620	2,592
108	300	600	1,080	1,728	2,700

Table 94. DFT Block Signals
Signal	Direction	Description
`v`	Input	Indicates if the input data is valid. Assert this Boolean signal when input data is valid. If Low Latency Implementation parameter is turned on, the valid input must remain high from the first input of a DFT operation to the last. If Low Latency Implementation parameter is turned off, any invalid (`v` deasserted) cycles during a DFT operation are ignored.
`cmd`	Input	An encoding of the size of the current DFT. In DFT/IDFT dynamic mode, an extra MSB indicates whether to calculate a DFT (0) or an IDFT (1). The size of the DFT and DFT/IDFT mode, if appropriate, must be specified at the same time (cycle) as a valid `sop` signal. The value of `cmd` is ignored at all other times. When all 53 sizes are supported, in DFT-only mode, a 6-bit integer encodes the size of the DFT currently input. In dynamic DFT/IDFT-mode, it is a 7-bit integer. The bottom 6 bits encode the size of the current DFT/IDFT, the MSB signifies whether to calculate a DFT or an IDFT. The DFT specifies the size of the DFT by specifying the zero-based index of the required size in the FFT Size Table parameter. For example, where FFT Size Table is [12 24 36], 0 specifies size 12 and 1 specifies size 24.
`sop`	Input	A start-of-packet Boolean signal that pulses high on the first (and only the first) valid input of a DFT/IDFT. Assert `sop` to indicate the first data input of a DFT. The generated RTL requires at least one cycle gap between the reset deasserting and the first `sop` signal.
`data`	Input	A complex input data signal of the user-specified type (Input Type).
`v`	Output	v indicates if the output data is valid. This boolean signal isasserted for valid output data.
`cmd`	Output	An encoding of the size of the current DFT. In DFT/IDFT dynamic mode, an extra MSB indicates whether the current output is a DFT (0) or an IDFT (1). When all 53 sizes are supported, `cmd` is a 6-bit signal with the size of the current DFT. In dynamic DFT/IDFT mode `cmd` is a 7-bit signal with the current DFT/iDFT size and status of the DFT/IDFT. Specify the size of the DFT by specifying the zero-based index of the required size in the FFT Size Table vector. For example, where FFT Size Table is [12 24 36], 0 specifies size 12 and 1 specifies size 24.
`sop`	Output	A start-of-packet Boolean signal that pulses high on the first (and only the first) valid output of a DFT/IDFT.
`pos`	Output	Indicates the natural order position of the current input. The data outputs are produced in radix-reversed order. Writing each sample to memory at location `pos` means the memory contains the samples in natural order.
`data`	Output	A full word growth complex output signal. When all 53 sizes are specified, DSP builder calculates the type of this signal by applying 13 bits of word-growth to the input data type.

Table 95. DFT Block Parameters
Parameter	Description
FFT Size Table	Specify the list of DFT sizes to support, in the form of a MATLAB vector. For example, [12 24 36]. Allowed sizes are specified in the DFT Block Supported Sizes table.
Input Type	Specify the fixed-point MATLAB type of the input data. For example, fixdt(1,16,15)
Twiddle Type	Specify the fixed-point MATLAB type of the twiddle constants, and the multiplicative constants needed for radix-3 and radix-5 FFT stages. For example, fixdt(1,18,17)
Support dynamic DFT/IDFT	When false, the block only supports DFTs; when true it also supports IDFTs.
Low Latency implementation	Select to choose low latency implementation. If you choose the low latency implementation the data valid input `v` must remain high from the first input of a DFT operation to the last.

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DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

15.2.1. DFT (DFT)