Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
Public

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3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor

Based on the values you set, the Serial Lite III Streaming Intel® FPGA IP parameter editor automatically calculates the rest of the parameters, and provides you with the following values or information:

  • Input data rate per lane
  • Transceiver data rate per lane
  • A list of feasible transceiver reference clock frequencies, one of which you select to provide to the core
Important: If your design targets Stratix® V or Arria® V GZ devices, you cannot migrate your design to Intel® Arria® 10 , Intel® Cyclone® 10 GX , and Intel® Stratix® 10 devices automatically. For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the transceiver reconfiguration functionality is embedded inside the transceivers. Therefore, you must re-instantiate the IP to target Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. For Intel® Stratix® 10 devices, you must re-instantiate the IP to target specific transceiver tiles due to the transceiver architecture differences. You cannot migrate your design from Intel® Stratix® 10 L-tile/H-Tile devices to Intel® Stratix® 10 E-Tile devices.