BCH IP Core: User Guide

Download PDF
ID 683320
Date 2/13/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the BCH IP Core 2. BCH IP Core Getting Started 3. BCH IP Core Functional Description 4. Document Revision History A. BCH IP Core Document Archive
1. About the BCH IP Core x
1.1. Intel® DSP IP Core Features 1.2. BCH IP Core Features 1.3. DSP IP Core Device Family Support 1.4. BCH IP Core Release Information 1.5. DSP IP Core Verification 1.6. BCH IP Core Performance and Resource Utilization
2. BCH IP Core Getting Started x
2.1. Installing and Licensing IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing IP Cores x
2.1.1. OpenCore Plus IP Evaluation 2.1.2. BCH IP Core OpenCore Plus Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. BCH IP Core Functional Description x
3.1. BCH IP Core Encoder 3.2. BCH IP Core Decoder 3.3. BCH IP Core Parameters 3.4. BCH IP Core Interfaces and Signals
3.4. BCH IP Core Interfaces and Signals x
3.4.1. Avalon-ST Interfaces in DSP IP Cores
1. About the BCH IP Core
2. BCH IP Core Getting Started
3. BCH IP Core Functional Description
4. Document Revision History
A. BCH IP Core Document Archive

3.4. BCH IP Core Interfaces and Signals

Table 8.  Clock and Reset Signals
Name Avalon-ST Type Direction Description
clk clk Input The main system clock. The whole IP core operates on the rising edge of clk .
reset reset_n Input An active low signal that resets the entire system when asserted. You can assert this signal asynchronously. However, you must deassert it synchronous to the clk_clk signal. When the IP core recovers from reset, ensure that the data it receives is a complete packet.
Table 9.   Avalon-ST Input and Output Interface Signals
Name Avalon-ST Type Direction Description
ready ready Output Data transfer ready signal to indicate that the sink is ready to accept data. The sink interface drives the ready signal to control the flow of data across the interface. The sink interface captures the data interface signals on the current clk rising edge.
data_in[] data Input Data input for each codeword, symbol by symbol. Valid only when you assert the in_valid signal.
data_out data Output Contains decoded output when the IP core asserts the out_valid signal. The corrected symbols are in the same order that they are entered.
eop_in eop Input End of packet (codeword) signal.
eop_out eop Output End of packet (codeword) signal. This signal indicates the packet boundaries on the data_in[] bus. When the IP core drives this signal high, it indicates that the end of packet is present on the data_in[] bus. The IP core asserts this signal on the last transfer of every packet.
in_error error Input Error signal. Specifies if the input data symbol is an error and whether the decoder can consider it as an erasure. Erasures-supporting decoders only.
load valid Input Data valid signal to indicate the validity of the data signals. When you assert the in_valid signal, the Avalon-ST data interface signals are valid. When you deassert the in_valid signal, the Avalon-ST data interface signals are invalid and must be disregarded. You can assert the in_valid signal whenever data is available. However, the sink only captures the data from the source when the IP core asserts the in_ready signal.
number_of_errors error Output Indicates the number of errors (decoder only). Valid when the IP core asserts eop_out .
       
sop_in sop Input Start of packet (codeword) signal.
sop_out sop Output Start of packet (codeword) signal. This signal indicates the codeword boundaries on the data_in[] bus. When the IP core drives this signal high, it indicates that the start of packet is present on the data_in[] bus. The IP core asserts this signal on the first transfer of every codeword.
sink_ready ready Input Data transfer ready signal to indicate that the downstream module is ready to accept data. The source provides new data (if available) when you assert the sink_ready signal and stops providing new data when you deassert the sink_ready signal. If the source is unable to provide new data, it deasserts valid_out for one or more clock cycles until it is prepared to drive valid data interface signals.
valid_out valid Output Data valid signal. The IP core asserts the valid_out signal high, whenever a valid output is on data_out ; the IP core deasserts the signal when there is no valid output on data_out .
For IP cores generated within Qsys, all signals are in an Avalon-ST interface. For encoders:
  • Input port:0 to datawidthdata_in
  • Output port:0 to datawidthdata_out
For decoders:
  • Input port:0 to datawidthdata_in
  • Output port:0 to datawidth+number_errors | data_out

Section Content
Avalon-ST Interfaces in DSP IP Cores

Level Two Title