BCH IP Core: User Guide

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ID 683320
Date 2/13/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the BCH IP Core 2. BCH IP Core Getting Started 3. BCH IP Core Functional Description 4. Document Revision History A. BCH IP Core Document Archive
1. About the BCH IP Core x
1.1. Intel® DSP IP Core Features 1.2. BCH IP Core Features 1.3. DSP IP Core Device Family Support 1.4. BCH IP Core Release Information 1.5. DSP IP Core Verification 1.6. BCH IP Core Performance and Resource Utilization
2. BCH IP Core Getting Started x
2.1. Installing and Licensing IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing IP Cores x
2.1.1. OpenCore Plus IP Evaluation 2.1.2. BCH IP Core OpenCore Plus Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. BCH IP Core Functional Description x
3.1. BCH IP Core Encoder 3.2. BCH IP Core Decoder 3.3. BCH IP Core Parameters 3.4. BCH IP Core Interfaces and Signals
3.4. BCH IP Core Interfaces and Signals x
3.4.1. Avalon-ST Interfaces in DSP IP Cores
1. About the BCH IP Core
2. BCH IP Core Getting Started
3. BCH IP Core Functional Description
4. Document Revision History
A. BCH IP Core Document Archive

3.1. BCH IP Core Encoder

The BCH encoder has a parallel architecture with an input and output of d data bits. When the encoder receives data symbols, it generates check symbols for a given codeword and sends the input codeword with the check symbols to the output interface. The encoder uses backpressure on the upstream component when it generates the check symbols.
Figure 6. Encoder Timing

The ready signal indicates that the encoder can accept incoming stream. On the clk rising edge, if the encoder ready signal is high, send input data stream via data_in port and assert load high to indicate valid input data. Assume the full message word needs X clock signals. When this input process reaches X-1 clock cycles, the encoder ready signal goes low. At the next clk rising edge, the encoder accepts the input from data_in port, and the encoder receives the full message word. Before the ready signal returns to high again, the encoder does not accept new input data. When valid_out signal is asserted high, output encoded codeword is valid at the data_out port. At the first clock cycle where the output data is valid, sop_out is asserted high for only one cycle, indicating the start of packet. The IP core has forward and back pressure, which you can control with the ready and sink_ready signal. Assert the sop_in and eop_in signals correctly at the clock cycle, i.e. the first and last clock cycle of the input codeword.

Shortened Codewords

The BCH IP core supports shortened codewords. A shortened codeword contains fewer symbols than the maximum value of N, which is 2M –1, where N is the total number of symbols per codeword and M is the number of bits per symbol. A shortened codeword is mathematically equivalent to a maximum-length code with the extra data symbols at the start of the codeword set to 0. For example, (220,136) is a shortened codeword of (255,171). Both of these codewords use the same number of check symbols, 11. To use shortened codewords with the decoder, use the parameter editor to set the codeword length to the correct value.

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