AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel® Arria® 10 Devices

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ID 683319
Date 5/08/2017
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Document Table of Contents x
1. AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel Arria 10 Devices
1. AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel Arria 10 Devices x
1.1. Setting up the Hardware 1.2. Running the Multi Rate (Up to 12G) SDI II with External VCXO Reference Design 1.3. Reference Design Components 1.4. Compiling the Design and Configuring the FPGA 1.5. Document Revision History
1.2. Running the Multi Rate (Up to 12G) SDI II with External VCXO Reference Design x
1.2.1. Receiver 1.2.2. Parallel Loopback
1.3. Reference Design Components x
1.3.1. Channel Data Rate
1. AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel Arria 10 Devices

1.1. Setting up the Hardware

Complete the steps in the following topics to set up the hardware for the multi rate SDI II with external VCXO reference design.

Hardware and Software Requirements

The multi rate SDI II with external VCXO reference design requires the following hardware and software:

  • Arria 10 GX FPGA Development Board (10AX115S3F45E2SGE3)
  • VIDIO™ FMC Development Module VIDIO-12G-A (Nextera FMC daughter card)
  • BNC plug to BNC plug cables
  • 12G SDI Signal Analyzer
  • 12G SDI Signal Generator
  • Quartus® Prime software version 16.0

Connecting the Hardware

Figure 2.  Hardware Setup


Plug the Nextera FMC daughter card to the FMC connector port B. Connect the development board to 12V DC input (J13) power supply.

Setting the DIP Switches

Set the DIP switches of the development board as specified below.

Table 1.  DIP Switch Control Settings
DIP Switch Schematic Signal Name Description Setting
SW3

(PCIe*)

 1 X1 ON for PCIe X1 ON
2 X4 ON for PCIe X4 ON
3 X8 ON for PCIe X8 ON
4 — OFF for 1.35 V MEM_VDD power rail OFF
SW4

(JTAG)

 1 Arria 10 OFF to enable the Arria 10 device in the JTAG chain OFF
2 MAX V OFF to enable the MAX V device in the JTAG chain OFF
3 FMCA ON to bypass the FMCA connector in the JTAG chain ON
4 FMCB ON to bypass the FMCB connector in the JTAG chain ON
SW5

(Configuration) 1

1 MSEL0 ON for MSEL0 = 1; for FPP standard mode OFF
2 MSEL1 ON for MSEL1 = 0; for FPP standard mode OFF
3 MSEL2 ON for MSEL2 = 0; for FPP standard mode ON
4 VIDEN OFF for enabling VID_EN for the Smart Voltage ID (SmartVID) feature ON
SW6

(Board Settings)

1 CLK_SEL

ON for 100 MHz on-board clock oscillator selection

OFF for SMA input clock selection

 ON
2 CLK_EN OFF for setting CLK_ENABLE signal high to the MAX V device OFF
3 Si516_FS

ON for setting the SDI REFCLK frequency to 148.35 MHz

OFF for setting the SDI REFCLK frequency to 148.5 MHz

 OFF
4 FACTORY

ON to load factory image from flash

OFF to load user hardware from flash

 ON
5 RZQ_B2K

ON for setting RZQ resistor of Bank 2K to 99.17 ohm

OFF for setting RZQ resistor of Bank 2K to 240 ohm

 OFF
Figure 3. DIP Switches

Jumper Settings

Figure 4.  Jumper Settings on the Nextera FMC Daughter Card


Note: Refer to the jumper settings to change the jumper (J8) position before you switch between PAL and NTSC video format. You must press the push button (PB0) to trigger a device (LMK03328) power cycling through the PDN pin every time you change the jumper (J8) position.
Table 2.  Jumper SettingsSet the jumper position of the Nextera daughter card as specified below.
Jumper Block Description Setting
J7 Programming header.  
J8 To switch frequency between PAL and NTSC for TX channel.
  • Pin 1–2 = 297 MHz
  • Pin 2–3 = 297/1.001 MHz
  • 1–2 for PAL
  • 2–3 for NTSC
J9 To select SDI or IP mode. Pin 1-2 =SDI Mode; pin 2-3=IP mode
  • Pin 1–2 = SDI Mode
  • Pin 2–3 = IP mode
 1–2

Port Assignments

Table 3.  SDI Channels and PortsFPGA pins and physical ports for SDI TX/RX channels
Transceiver Channel FPGA Pin Physical Port on Nextera Daughter Card
Channel 0 TX AB1/AB2 SDI_OUT (J2)
Channel 0 RX Y5/Y6 SDI_IN (J1)

Clock Input

Table 4.  Input Clock Frequency and FPGA PinsInput clock frequency and FPGA pins for the multi rate SDI II reference design.
Hardware Input Clock Frequency FPGA Input Pin Description
Arria 10 GX development board 100 MHz F23/G23 As the channel 0 reconfig clock
Arria 10 GX development board 148.5/148.35 MHz L37/L38 As the reference clock for channel 0 rx_coreclk and rx_cdr_refclk0, and RX PHY reset controller.
Nextera FMC daughter card 297/296.7 MHz W8/W7 As the reference clock for channel 0 fPLL, and TX PHY reset controller
1 Set the MSEL [2:0] bits according to your chosen configuration scheme.
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