AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel® Arria® 10 Devices

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ID 683319
Date 5/08/2017
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Document Table of Contents
Document Table of Contents x
1. AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel Arria 10 Devices
1. AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel Arria 10 Devices x
1.1. Setting up the Hardware 1.2. Running the Multi Rate (Up to 12G) SDI II with External VCXO Reference Design 1.3. Reference Design Components 1.4. Compiling the Design and Configuring the FPGA 1.5. Document Revision History
1.2. Running the Multi Rate (Up to 12G) SDI II with External VCXO Reference Design x
1.2.1. Receiver 1.2.2. Parallel Loopback
1.3. Reference Design Components x
1.3.1. Channel Data Rate
1. AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel Arria 10 Devices

1.2.1. Receiver

To run the test, connect an SDI signal generator to the receiver input, SDI_IN (J1), of channel 0.

This test uses the following user LEDs to indicate the respective conditions:
  • D8, D9, and D10 indicate the receiver signal standard.
  • D7 illuminates when the CRC error signal for channel 0 is asserted.
  • D6 illuminates when the trs_locked signal for channel 0 is asserted.
  • D5 illuminates when the frame_locked signal for channel 0 is asserted.
Figure 5. User LEDs


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