Low Latency 100G Ethernet Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683315
Date 12/14/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 100G Ethernet Intel Agilex FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling the Compilation-Only Project 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the Low Latency 100G Ethernet Intel Agilex FPGA Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
1.6. Testing the Low Latency 100G Ethernet Intel Agilex FPGA Intel® FPGA IP Design in Hardware x
1.6.1. Testing the Hardware Design Example using Ethernet Toolkit
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Simulation 2.4. Design Example Behavior 2.5. Design Example Registers 2.6. Design Example Interface Signals
2.5. Design Example Registers x
2.5.1. Packet Generator Programming Sequence
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 100G Ethernet Intel Agilex FPGA IP Design Example User Guide

1.2. Directory Structure

The Low Latency 100G Ethernet Intel® Agilex™ FPGA IP core design example file directories contain the following generated files for the design example.

Figure 4. Directory Structure for the Generated Design Example
  • The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
  • The compilation-only example design is located in <design_example_dir>/compilation_test_design.
  • The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design
    Note: The hardware design example is not available in the Intel® Quartus® Prime Pro Edition software 20.3 version. The generated hardware configuration and test files are for internal use only.
    .
Table 2.  Directory and File Descriptions

File Names

Description

alt_e100fmh.qpf Intel® Quartus® Prime project file.
alt_e100fmh.qsf Intel® Quartus® Prime project settings file.
alt_e100fmh.sdc Synopsys* Design Constraints file. You can copy and modify this file for your own Low Latency 100G Ethernet Intel® Agilex™ FPGA IP design.
alt_e100fmh.v Top-level Verilog HDL design example file.
common/ Hardware design example support files.
hwtest/main.tcl

Main file for accessing System Console.
Level Two Title