1.1. Overview
The Intel® FPGA implements Secure Device Manager (SDM) architecture starting with Intel® Stratix® 10 devices and all future FPGA devices. The SDM consists of the triple-redundant lockstep processors and other components described in the Intel® Stratix® 10 Configuration User Guide.
- JTAG interface
- HPS interface
- FPGA core interface using soft IPs
This application note only provides information on accessing the SDM via the JTAG interface.
For information on accessing the SDM from the FPGA core interface, refer to the Mailbox Client Intel® FPGA IP User Guide.
The figure below is a block diagram of the Secure Device Manager hardware, showing the various interfaces the SDM can use to communicate with devices.