2.7. Hardware Setup
The HDMI Intel® FPGA IP design example is HDMI 2.0 capable and performs a loop-through demonstration for a standard HDMI video stream.
To run the hardware test, connect an HDMI-enabled device—such as a graphics card with HDMI interface—to the Transceiver Native PHY RX block, and the HDMI sink input.
- The HDMI sink decodes the port into a standard video stream and sends it to the clock recovery core.
- The HDMI RX core decodes the video, auxiliary, and audio data to be looped back in parallel to the HDMI TX core through the DCFIFO.
- The HDMI source port of the FMC daughter card transmits the image to a monitor.
Note: If you use another Intel FPGA development board, you must change the device assignments and the pin assignments. The transceiver analog setting is tested for the Cyclone® 10 GX FPGA development kit and Bitec HDMI 2.0 daughter card. You may modify the settings for your own board.
LEDs | Function |
---|---|
user_dipsw[0] |
|
user_pb[0] | Press once to perform system reset. |
user_pb[1] | Press once to toggle the HPD signal to the standard HDMI source. |
user_pb[2] |
|
USER_LED[0] |
RX HDMI PLL lock status or RX transceiver ready status.
|
USER_LED[1] |
RX HDMI core lock status.
|
USER_LED[2] |
TX HDMI PLL lock status, TX transceiver PLL lock status, or TX transceiver ready status.
|
USER_LED[3] |
TX or RX oversampling status.
|