HDMI Cyclone® 10 GX FGPA IP Design Example User Guide

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ID 683309
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices 2. HDMI Design Example 3. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for HDMI Cyclone® 10 GX FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI Design Example x
2.1. HDMI RX-TX Retransmit Design Block Diagram 2.2. Design Components 2.3. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.4. Clocking Scheme 2.5. Interface Signals 2.6. Design RTL Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices
2. HDMI Design Example
3. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for HDMI Cyclone® 10 GX FPGA IP Design Example User Guide

1.2. Hardware and Software Requirements

Intel uses the following hardware and software to test the design example.

Hardware

  • Cyclone® 10 GX FPGA Development Kit
  • HDMI Source (Graphics Processor Unit (GPU))
  • HDMI Sink (Monitor)
  • Bitec HDMI FMC 2.0 daughter card (Revision 11)
  • HDMI cables

Software

  • Quartus® Prime Pro Edition version 20.3 and later (for hardware testing)
  • Ashling RiscFree* integrated development environment (IDE) for Intel FPGAs
  • ModelSim* - Intel® FPGA Edition, ModelSim* - Intel® FPGA Starter Edition, , Riviera-PRO* , VCS* (Verilog HDL only)/ VCS* MX, or Xcelium* Parallel simulator
Level Two Title