HDMI Cyclone® 10 GX FGPA IP Design Example User Guide

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ID 683309
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices 2. HDMI Design Example 3. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for HDMI Cyclone® 10 GX FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI Design Example x
2.1. HDMI RX-TX Retransmit Design Block Diagram 2.2. Design Components 2.3. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.4. Clocking Scheme 2.5. Interface Signals 2.6. Design RTL Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices
2. HDMI Design Example
3. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for HDMI Cyclone® 10 GX FPGA IP Design Example User Guide

1.4. Simulating the Design

The HDMI testbench simulates a serial loopback design from a TX instance to an RX instance. Internal video pattern generator, audio sample generator, sideband data generator, and auxiliary data generator modules drive the HDMI TX instance and the serial output from the TX instance connects to the RX instance in the testbench.
Figure 4. Design Simulation Flow
  1. Go to the desired simulation folder.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
  3. Analyze the results.
    Table 4.  Steps to Run Simulation
    Simulator Working Directory Instructions
    Riviera-PRO* /simulation/aldec
    In the command line, type 
    vsim -c -do aldec.do
    ModelSim* /simulation/mentor
    In the command line, type 
    vsim -c -do mentor.do
    VCS* /simulation/synopsys/vcs
    In the command line, type 
    source vcs_sim.sh
    VCS* MX /simulation/synopsys/vcsmx
    In the command line, type 
    source vcsmx_sim.sh
    Xcelium* Parallel /simulation/xcelium In the command line, type 
    source xcelium_sim.sh
    A successful simulation ends with the following message: 
    # SYMBOLS_PER_CLOCK 	= 2
# VIC               	= 4
# FRL_RATE          	= 0
# BPP               	= 0
# AUDIO_FREQUENCY (kHz)  = 48
# AUDIO_CHANNEL     	= 8
# Simulation pass
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