HDMI Cyclone® 10 GX FGPA IP Design Example User Guide

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ID 683309
Date 4/29/2024
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices 2. HDMI Design Example 3. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for HDMI Cyclone® 10 GX FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI Design Example x
2.1. HDMI RX-TX Retransmit Design Block Diagram 2.2. Design Components 2.3. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.4. Clocking Scheme 2.5. Interface Signals 2.6. Design RTL Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices
2. HDMI Design Example
3. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for HDMI Cyclone® 10 GX FPGA IP Design Example User Guide

1.3. Generating the Design

Use the HDMI Intel® FPGA IP parameter editor in the Quartus® Prime Pro Edition software to generate the design examples.
Starting with the Quartus® Prime Pro Edition software version 24.1, you need to install Cmake version 3.14.2 onward prior to generating your design example. Cmake is needed for software generation and rebuilding.
Note: You need a Nios® V evaluation license. Refer to the Nios® V Processor Licensing topic in the Nios® V Embedded Processor Design Handbook.
Figure 3. Generating the Design Flow
  1. Create a project targeting Cyclone® 10 GX device family and select the desired device.
  2. In the IP Catalog, locate and double-click HDMI Intel® FPGA IP . The New IP Variant or New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, configure the desired parameters for both TX and RX.
  6. On the Design Example tab, select Cyclone 10 HDMI RX-TX Retransmit.
  7. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
  8. For Generate File Format, select Verilog or VHDL.
  9. For Target Development Kit, select Cyclone® 10 GX FPGA Development Kit. If you select a development kit, then the target device (selected in step 4) changes to match the device on target board. For Cyclone® 10 GX FPGA Development Kit, the default device is 10CX220YF780E5G.
  10. Click Generate Example Design.
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