JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

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ID 683298
Date 7/29/2024
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Design Components 1.2.6. Clocking Scheme 1.2.7. Simulation 1.2.8. Design Example Files 1.2.9. Registers 1.2.10. Signals 1.2.11. Customizing the Design Example
1.2.5. Design Components x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker
1.2.5.1. Platform Designer System Component x
1.2.5.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.2. Parallel I/O 1.2.5.1.3. ATX PLL 1.2.5.1.4. Core PLL 1.2.5.1.5. SPI Master
1.2.7. Simulation x
1.2.7.1. Testbench
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.2.11.1. Modifying the JESD204B IP Core Parameters

The Platform Designer tool allows only a limited set of design examples to be generated based on the JESD204B IP core parameters selected.

Perform the following instructions to modify the JESD204B IP core parameters post-generation:

  1. Open the generated design example project in the Quartus® Prime software.
  2. Open the altjesd_ss_<data path>.qsys system in Platform Designer.
  3. In the System Contents tab, double-click the altjesd_<data path> module. This brings up the parameter editor that shows the current parameter settings of the JESD204B IP core.
  4. Modify the parameters of the JESD204B IP core module as per your system specifications. When you are done, save the Platform Designer system (File > Save).
    Note: The JESD204B IP core and transport layer imposes certain limits on the values that can be entered as parameters. Refer to the JESD204B Intel® FPGA IP User Guide for a complete listing of the legal parameter values.
  5. Click the Generate HDL to generate the HDL files needed for Quartus® Prime compilation.
  6. After the HDL generation is completed, click the Finish to save your settings and exit Platform Designer.
  7. You have to manually change the system parameters in the top level RTL file to match the parameters that you set in the Platform Designer project, if applicable. Open the top level RTL file (altera_jesd204_ed_<data path>.sv) in any text editor of your choice.
  8. Modify the system parameters at the top of the file to match the new JESD204B IP core settings in the Platform Designer project, if applicable.
  9. Save the file and compile the design in Quartus® Prime software as per the instructions in the Compiling and Testing the Design.
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