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1.1.4. Compiling and Testing the Design
The JESD204B parameter editor allows you to run the design example on a target development kit.
Perform the following steps to compile the design and program the development board:
- Launch the Quartus® Prime software and compile the design (Processing > Start Compilation).
The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
- Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
- If you are performing external FMC loopback test, attach the FMC loopback card to the FMC port connector.
- Launch the Clock Control application that is included with the development board, and set the clock settings according to the selected data rate.
Note: Refer to the Intel® Cyclone® 10 GX FPGA Development Kit documentation for more information on using the Clock Control application.
Table 3. Clock Setting Clock Name Clock Frequency device_clk Select the frequencies in the PLL/CDR Reference Clock Frequency drop down menu of the IP parameter editor.1 mgmt_clk 100 MHz Figure 4. Clock Control GUI SettingThis example shows the clock control GUI setting for 6.144 Gbps data rate. - Configure the FPGA on the development board with the generated programming file (.sof file) using the Quartus® Prime Programmer.
1 The design example uses 153.6 MHz clock frequency for designs with data rate of 6.144 Gbps.