JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

ID 683298
Date 7/29/2024
Public
Document Table of Contents

1.2.5. Design Components

The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.

Figure 7. JESD204B Design Example Block Diagram
  • Platform Designer system
    • JESD204B subsystem
    • JTAG to Avalon master bridge
    • Parallel I/O (PIO)
    • ATX PLL
    • Core PLL
    • PLL reconfiguration module (For transceiver dynamic reconfiguration enabled mode only)
    • Serial Port Interface (SPI)—master module
  • Test pattern generator (For duplex and simplex TX data path only)
  • Test pattern checker (For duplex and simplex RX data path only)
  • Assembler—TX transport layer (For duplex and simplex TX data path only)
  • Deassembler—RX transport layer (For duplex and simplex RX data path only)