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1.2.5. Design Components
The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.
Figure 7. JESD204B Design Example Block Diagram
- Platform Designer system
- JESD204B subsystem
- JTAG to Avalon master bridge
- Parallel I/O (PIO)
- ATX PLL
- Core PLL
- PLL reconfiguration module (For transceiver dynamic reconfiguration enabled mode only)
- Serial Port Interface (SPI)—master module
- Test pattern generator (For duplex and simplex TX data path only)
- Test pattern checker (For duplex and simplex RX data path only)
- Assembler—TX transport layer (For duplex and simplex TX data path only)
- Deassembler—RX transport layer (For duplex and simplex RX data path only)