JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

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ID 683298
Date 7/29/2024
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Design Components 1.2.6. Clocking Scheme 1.2.7. Simulation 1.2.8. Design Example Files 1.2.9. Registers 1.2.10. Signals 1.2.11. Customizing the Design Example
1.2.5. Design Components x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker
1.2.5.1. Platform Designer System Component x
1.2.5.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.2. Parallel I/O 1.2.5.1.3. ATX PLL 1.2.5.1.4. Core PLL 1.2.5.1.5. SPI Master
1.2.7. Simulation x
1.2.7.1. Testbench
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.2.5.3. Test Pattern Generator

Note: This module is only available in the design example when the duplex or simplex TX data path option is selected.

The test pattern generator generates either a parallel PRBS, alternate checkerboard, or ramp wave, and sends it to the transport layer during test mode. The test pattern generator is implemented in the top level RTL file, not in the Platform Designer project.

You can modify the test pattern generator RTL match your specifications. Furthermore, for parameters like M, S, N, and test mode, the test pattern generator shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core, affects the test pattern generator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR.

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