JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

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ID 683298
Date 7/29/2024
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Design Components 1.2.6. Clocking Scheme 1.2.7. Simulation 1.2.8. Design Example Files 1.2.9. Registers 1.2.10. Signals 1.2.11. Customizing the Design Example
1.2.5. Design Components x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker
1.2.5.1. Platform Designer System Component x
1.2.5.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.2. Parallel I/O 1.2.5.1.3. ATX PLL 1.2.5.1.4. Core PLL 1.2.5.1.5. SPI Master
1.2.7. Simulation x
1.2.7.1. Testbench
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.1.4.1. Board Connectivity

If you are performing hardware testing on the selected Intel development kits, generate the design example with the appropriate target development kit selected.

Refer to the instructions in Generating the Design.

Note: Running the hardware test with the design generated as-is is only possible when the JESD204B IP core is configured in duplex data path mode (i.e. with both TX and RX data paths present). Make your own modifications to the design to run the hardware test if generating a simplex data path design.
Table 4.   Intel® Cyclone® 10 GX FPGA Development Kit Board ConnectivityThe generated design has pre-assigned pins that target the relevant boards. The table describes the board connectivity of key design ports for all supported target development kits.
Port Name Port Description Board Component Component Description
global_rst_n Global reset S8 User PB0 push-button
device_clk Reference clock input U64 Si5332 clock generator (OUT1)
mgmt_clk Control clock U64 Si5332 clock generator (OUT6)
tx_serial_data TX serial data J7 FMC connector
rx_serial_data RX serial data J7 FMC connector
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