Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Public
Document Table of Contents

9.2.2. Configuration Space Bypass Mode

When you select Enable Configuration Space Bypass under the System Settings heading of the parameter editor, the Arria® V GZ Hard IP for PCI Express bypasses the Transaction Layer Configuration Space registers included as part of the hard IP, allowing you to substitute a custom Configuration Space implemented in soft logic. If you implement Configuration Space Bypass mode, the Configuration Shadow Extension Bus is not available. In Configuration Space Bypass mode, all received Type 0 configuration writes and reads are forwarded to the Avalon‑ST interface.

In Configuration Space Bypass mode, you must also implement all of the TLP BAR matching and completion tag checking in soft logic.

If you enable Configuration Space Bypass mode, you can implement the following features in soft logic:

  • Resizable BARs
  • Latency Tolerance Reporting
  • Multicast
  • Dynamic Power Allocation
  • Alternative Routing‑ID Interpretation (ARI)
  • Single Root I/O Virtualization (SR‑IOV)
  • Multi‑functions

The RX Buffer, Flow Control, DL and PHY layers from the Arria® V GZ Hard IP for PCI Express are retained in the Hard IP.

Figure 46. Configuration Space Bypass Mode

In Configuration Space Bypass Mode, the hard IP passes all well‑formed TLPs to the Application Layer using the Avalon-ST RX interface. The hard IP detects and drops malformed TLPs. Application Layer logic must detect and handle Unsupported Requests and Unexpected Completions. Application Layer logic must also generate all completions and messages and transmit them using the Avalon-ST TX interface.

In Configuration Space Bypass Mode, the Power Management, MSI and legacy interrupts, Completion Errors, and Configuration Interfaces are disabled inside the hard IP. You must implement these features in the Application Layer. You can use the LMI bus in Configuration Space Bypass mode to log the TLP header of the first error in the AER registers.